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Energy Efficient Approximate Multiplier for Error Resilient Applications.

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Title: Energy Efficient Approximate Multiplier for Error Resilient Applications.
Authors: Rasoju, Veerabadra Chary1 (AUTHOR) p20180105@hyderabad.bits-pilani.ac.in, Anil Kumar, Uppugunduru1 (AUTHOR) anilkumaruppugundur@gmail.com, Jonnalagadda, Aditya Anirudh1 (AUTHOR) f20200373@hyderabad.bits-pilani.ac.in, Veeramachaneni, Sreehari2 (AUTHOR) srihariy2k4@gmail.com, Ahmed, Syed Ershad1 (AUTHOR) syed@hyderabad.bits-pilani.ac.in
Source: Journal of Circuits, Systems & Computers. 7/30/2026, Vol. 35 Issue 12, p1-16. 16p.
Subjects: Logic design, Verilog (Computer hardware description language), Computer engineering, Fault tolerance (Engineering), Binary operations
Abstract: Approximate computing is an emerging paradigm in computer arithmetic aimed at improving power efficiency by substituting exact computations with approximate ones in applications such as data analytics, deep learning, signal processing and image processing. This work aims to design an approximate multiplication circuit for error resilient applications. This paper proposes an approximation technique and error-correction scheme for unsigned binary multiplication. The approximate multiplier, which is proposed in this paper, is divided into three regions — two approximate and one exact where approximation using OR gates takes place both column-wise and row-wise. The partial product (PP) bits on the most significant bit (MSB) side on the first three rows are approximated in addition to the PP bits on the least significant bit (LSB) side using OR gates instead of exact computation using compressors, saving precious hardware resources. The error due to the approximate region is mitigated using a simple yet efficient error correction scheme. Multiplier designs are implemented using Verilog HDL and synthesized using TSMC 90 nm process node. Hardware synthesis results indicate an improvement of up to 35% in the power-delay product (PDP) in the 8-bit circuit and an improvement of 59% in the 16-bit circuit compared to the existing designs without any significant compromise in the accuracy. [ABSTRACT FROM AUTHOR]
Copyright of Journal of Circuits, Systems & Computers is the property of World Scientific Publishing Company and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
FullText Text:
  Availability: 0
Header DbId: egs
DbLabel: Engineering Source
An: 193816500
AccessLevel: 6
PubType: Academic Journal
PubTypeId: academicJournal
PreciseRelevancyScore: 0
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  Data: Energy Efficient Approximate Multiplier for Error Resilient Applications.
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  Data: <searchLink fieldCode="AR" term="%22Rasoju%2C+Veerabadra+Chary%22">Rasoju, Veerabadra Chary</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> p20180105@hyderabad.bits-pilani.ac.in</i><br /><searchLink fieldCode="AR" term="%22Anil+Kumar%2C+Uppugunduru%22">Anil Kumar, Uppugunduru</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> anilkumaruppugundur@gmail.com</i><br /><searchLink fieldCode="AR" term="%22Jonnalagadda%2C+Aditya+Anirudh%22">Jonnalagadda, Aditya Anirudh</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> f20200373@hyderabad.bits-pilani.ac.in</i><br /><searchLink fieldCode="AR" term="%22Veeramachaneni%2C+Sreehari%22">Veeramachaneni, Sreehari</searchLink><relatesTo>2</relatesTo> (AUTHOR)<i> srihariy2k4@gmail.com</i><br /><searchLink fieldCode="AR" term="%22Ahmed%2C+Syed+Ershad%22">Ahmed, Syed Ershad</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> syed@hyderabad.bits-pilani.ac.in</i>
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  Data: <searchLink fieldCode="JN" term="%22Journal+of+Circuits%2C+Systems+%26+Computers%22">Journal of Circuits, Systems & Computers</searchLink>. 7/30/2026, Vol. 35 Issue 12, p1-16. 16p.
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  Data: <searchLink fieldCode="DE" term="%22Logic+design%22">Logic design</searchLink><br /><searchLink fieldCode="DE" term="%22Verilog+%28Computer+hardware+description+language%29%22">Verilog (Computer hardware description language)</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+engineering%22">Computer engineering</searchLink><br /><searchLink fieldCode="DE" term="%22Fault+tolerance+%28Engineering%29%22">Fault tolerance (Engineering)</searchLink><br /><searchLink fieldCode="DE" term="%22Binary+operations%22">Binary operations</searchLink>
– Name: Abstract
  Label: Abstract
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  Data: Approximate computing is an emerging paradigm in computer arithmetic aimed at improving power efficiency by substituting exact computations with approximate ones in applications such as data analytics, deep learning, signal processing and image processing. This work aims to design an approximate multiplication circuit for error resilient applications. This paper proposes an approximation technique and error-correction scheme for unsigned binary multiplication. The approximate multiplier, which is proposed in this paper, is divided into three regions — two approximate and one exact where approximation using OR gates takes place both column-wise and row-wise. The partial product (PP) bits on the most significant bit (MSB) side on the first three rows are approximated in addition to the PP bits on the least significant bit (LSB) side using OR gates instead of exact computation using compressors, saving precious hardware resources. The error due to the approximate region is mitigated using a simple yet efficient error correction scheme. Multiplier designs are implemented using Verilog HDL and synthesized using TSMC 90 nm process node. Hardware synthesis results indicate an improvement of up to 35% in the power-delay product (PDP) in the 8-bit circuit and an improvement of 59% in the 16-bit circuit compared to the existing designs without any significant compromise in the accuracy. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of Journal of Circuits, Systems & Computers is the property of World Scientific Publishing Company and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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RecordInfo BibRecord:
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        Value: 10.1142/S0218126626500854
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      – Code: eng
        Text: English
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        PageCount: 16
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      – SubjectFull: Logic design
        Type: general
      – SubjectFull: Verilog (Computer hardware description language)
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      – SubjectFull: Computer engineering
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      – SubjectFull: Fault tolerance (Engineering)
        Type: general
      – SubjectFull: Binary operations
        Type: general
    Titles:
      – TitleFull: Energy Efficient Approximate Multiplier for Error Resilient Applications.
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            NameFull: Rasoju, Veerabadra Chary
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            NameFull: Veeramachaneni, Sreehari
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            NameFull: Ahmed, Syed Ershad
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              Text: 7/30/2026
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              Y: 2026
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