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Hardware-efficient custom floating-point dot-product processor for LSTM.

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Title: Hardware-efficient custom floating-point dot-product processor for LSTM.
Authors: Venkatesh, Shreya1 (AUTHOR), Sindhu, R1 (AUTHOR), Hallur, Ashish G1 (AUTHOR), Sharma, Karra Shivam1 (AUTHOR), V, Arunachalam1 (AUTHOR) varunachalam@vit.ac.in
Source: International Journal of Electronics Letters. Jun2026, Vol. 14 Issue 2, p242-254. 13p.
Subjects: Long short-term memory, Floating-point arithmetic, Recurrent neural networks, Classification algorithms, Arithmetic
Abstract: This paper presents a hardware-efficient implementation of dot-product operations tailored for Long Short-Term Memory (LSTM) Recurrent Neural Networks (RNNs) using custom floating-point (CFP) format. The proposed design introduces a precision-aware arithmetic scheme that balances accuracy with hardware efficiency to address the computational and power demands of neural computations, especially in resource-constrained environments. The 11-bit (< 1-bit sign> < 6-bit exponent> < 4-bit mantissa>) CFP format extends the exponent range by a factor of 2 and achieves a dynamic range that is 15 times wider while preserving classification accuracy. An 11-bit CFP multiply-accumulate (MAC) unit is designed, and an FSM-controlled dot-product is implemented. Using this, the dense layer of an LSTM-based binary classification model was implemented. The design achieved 86.96% test accuracy with the IMDB dataset. The dot-product processor was synthesised using a TSMC 65 nm library and required a hardware area of 2029.60 µm2, consuming 0.374 mW at 500 MHz. [ABSTRACT FROM AUTHOR]
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Database: Engineering Source
Description
Abstract:This paper presents a hardware-efficient implementation of dot-product operations tailored for Long Short-Term Memory (LSTM) Recurrent Neural Networks (RNNs) using custom floating-point (CFP) format. The proposed design introduces a precision-aware arithmetic scheme that balances accuracy with hardware efficiency to address the computational and power demands of neural computations, especially in resource-constrained environments. The 11-bit (< 1-bit sign> < 6-bit exponent> < 4-bit mantissa>) CFP format extends the exponent range by a factor of 2 and achieves a dynamic range that is 15 times wider while preserving classification accuracy. An 11-bit CFP multiply-accumulate (MAC) unit is designed, and an FSM-controlled dot-product is implemented. Using this, the dense layer of an LSTM-based binary classification model was implemented. The design achieved 86.96% test accuracy with the IMDB dataset. The dot-product processor was synthesised using a TSMC 65 nm library and required a hardware area of 2029.60 µm2, consuming 0.374 mW at 500 MHz. [ABSTRACT FROM AUTHOR]
ISSN:21681724
DOI:10.1080/21681724.2026.2620382