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Power Supply Noise Aware Amplification in Voltage-Controlled Oscillator and Phase Locked Loop fed MOS Operational Amplifiers.

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Title: Power Supply Noise Aware Amplification in Voltage-Controlled Oscillator and Phase Locked Loop fed MOS Operational Amplifiers.
Authors: Karthik, G. V. Teja1 (AUTHOR), Ruthvik, Gogineni1 (AUTHOR), Srikanth Reddy, Meeniga1 (AUTHOR), Das, Naren2 (AUTHOR), Gollapudi, Sai Krishna Santosh1 (AUTHOR), Deb, Debajit1 (AUTHOR) debajitdeb12pec018@gmail.com
Source: Journal of Circuits, Systems & Computers. 10/1/2026, Vol. 35 Issue 17, p1-26. 26p.
Subjects: Phase-locked loops, Operational amplifiers, Voltage-controlled oscillators, Electric noise, Signal filtering, Phase noise
Abstract: This paper investigated the effect of supply noise on Phase-Locked Loop integrated with an operational amplifier, designed and implemented using the 90 nm generic library in Cadence. Effect of supply noise has been analyzed for each analog block of a single-ended operational transconductance amplifier circuit. To ensure minimal impact of supply noise on the current replication mechanism, low noise cascode current mirrors have been employed for biasing the amplifier. The current source of the mirror has been replaced with a diode-connected PMOS to minimize the transfer of supply noise to internal nodes. The input of the first stage operational amplifier is used as the supply for the second stage through low-pass filters. The capacitors in the filters have been replaced with equivalent MOSFETs (switch off mode) to enable low-power operation. This approach has effectively eliminated amplification errors caused by noise. Input AC sources have been substituted with proposed voltage-controlled oscillators to enable DC control and low-power amplifier operation. A supply noise bypass circuit has been proposed, which converts the negative sensitivity of the frequency response to positive sensitivity under high supply noise conditions. A Phase-Locked Loop (PLL) has been designed to ensure that the phase difference remains unaffected by the slow current draw of the inverter blocks in the VCO. This resulted in significantly high amplification, even in the presence of high supply noise. An interesting reduction of RMS jitter (by ∼ 60%) at output PLL node with high package inductance also indicates reduced phase error at higher supply noise. The noise aware PLL fed OP-AMP design has been found to dissipate ∼ 120 μ W power which is significantly smaller with recent low power works with similar input conditions. [ABSTRACT FROM AUTHOR]
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Database: Engineering Source
Description
Abstract:This paper investigated the effect of supply noise on Phase-Locked Loop integrated with an operational amplifier, designed and implemented using the 90 nm generic library in Cadence. Effect of supply noise has been analyzed for each analog block of a single-ended operational transconductance amplifier circuit. To ensure minimal impact of supply noise on the current replication mechanism, low noise cascode current mirrors have been employed for biasing the amplifier. The current source of the mirror has been replaced with a diode-connected PMOS to minimize the transfer of supply noise to internal nodes. The input of the first stage operational amplifier is used as the supply for the second stage through low-pass filters. The capacitors in the filters have been replaced with equivalent MOSFETs (switch off mode) to enable low-power operation. This approach has effectively eliminated amplification errors caused by noise. Input AC sources have been substituted with proposed voltage-controlled oscillators to enable DC control and low-power amplifier operation. A supply noise bypass circuit has been proposed, which converts the negative sensitivity of the frequency response to positive sensitivity under high supply noise conditions. A Phase-Locked Loop (PLL) has been designed to ensure that the phase difference remains unaffected by the slow current draw of the inverter blocks in the VCO. This resulted in significantly high amplification, even in the presence of high supply noise. An interesting reduction of RMS jitter (by ∼ 60%) at output PLL node with high package inductance also indicates reduced phase error at higher supply noise. The noise aware PLL fed OP-AMP design has been found to dissipate ∼ 120 μ W power which is significantly smaller with recent low power works with similar input conditions. [ABSTRACT FROM AUTHOR]
ISSN:02181266
DOI:10.1142/S0218126626501458