Suppressing Gate-Induced Drain Leakage with an Asymmetric Gate Design in HiPco CNT FETs.
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| Title: | Suppressing Gate-Induced Drain Leakage with an Asymmetric Gate Design in HiPco CNT FETs. |
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| Authors: | Ma, Hui1,2,3 (AUTHOR), Gu, Senbiao1,2,3 (AUTHOR), Zhai, Minglong2,3 (AUTHOR), Liu, Honggang1,2,4 (AUTHOR) liuhonggang@pku.edu.cn |
| Source: | Nanomaterials (2079-4991). Jun2026, Vol. 16 Issue 11, p653. 13p. |
| Subjects: | Carbon nanotube field effect transistors, Quantum tunneling, Transistors, Nanoelectronics, Single walled carbon nanotubes |
| Abstract: | Carbon nanotube field-effect transistors (CNT FETs) hold great promise for extending Moore's Law, yet their performance is critically limited by excessive off-state leakage, caused by band-to-band tunneling (BTBT) in narrow bandgap CNT channels. In this work, we overcome this long-standing bottleneck by introducing a co-design strategy that integrates a small-diameter HiPco CNT channel with a novel asymmetric gate architecture. This approach strategically reshapes the channel electrostatics to simultaneously suppress the gate-induced drain leakage (GIDL) effect and preserve excellent carrier transport. The efficacy of this strategy is rigorously validated through calibrated technology computer-aided design (TCAD) simulations for both NMOS and PMOS operation, demonstrating an ultralow off-current of 10 fA/µm, an on-current of 1.08 mA/µm, and a record on–off ratio of 1.1 × 1011 for back-gated CNTFETs at the 90 nm node. The design exhibits outstanding scalability: at the scaled 28 nm node with a supply voltage of 0.7 V, the PMOS device achieves 3 mA/µm on-current and 6 pA/µm off-current, maintaining an on–off ratio of 5 × 108. This work establishes a scalable pathway toward femtoampere-level CNT CMOS, addressing the static power challenge in future nano-electronics. [ABSTRACT FROM AUTHOR] |
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| Database: | Engineering Source |
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| Abstract: | Carbon nanotube field-effect transistors (CNT FETs) hold great promise for extending Moore's Law, yet their performance is critically limited by excessive off-state leakage, caused by band-to-band tunneling (BTBT) in narrow bandgap CNT channels. In this work, we overcome this long-standing bottleneck by introducing a co-design strategy that integrates a small-diameter HiPco CNT channel with a novel asymmetric gate architecture. This approach strategically reshapes the channel electrostatics to simultaneously suppress the gate-induced drain leakage (GIDL) effect and preserve excellent carrier transport. The efficacy of this strategy is rigorously validated through calibrated technology computer-aided design (TCAD) simulations for both NMOS and PMOS operation, demonstrating an ultralow off-current of 10 fA/µm, an on-current of 1.08 mA/µm, and a record on–off ratio of 1.1 × 1011 for back-gated CNTFETs at the 90 nm node. The design exhibits outstanding scalability: at the scaled 28 nm node with a supply voltage of 0.7 V, the PMOS device achieves 3 mA/µm on-current and 6 pA/µm off-current, maintaining an on–off ratio of 5 × 108. This work establishes a scalable pathway toward femtoampere-level CNT CMOS, addressing the static power challenge in future nano-electronics. [ABSTRACT FROM AUTHOR] |
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| ISSN: | 20794991 |
| DOI: | 10.3390/nano16110653 |
