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On-chip SRAM macro with 0.45μW/Mbit-leakage data retention using simultaneous control of source-line and body-line biasing.

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Title: On-chip SRAM macro with 0.45μW/Mbit-leakage data retention using simultaneous control of source-line and body-line biasing.
Authors: Jo, Hyejin1 (AUTHOR), Lee, Jaesung1 (AUTHOR), Yun, Dai1 (AUTHOR), Mun, Jihwan1 (AUTHOR), Min, Kyeong-Sik1 (AUTHOR) mks@kookmin.ac.kr
Source: Integration: The VLSI Journal. Jul2026, Vol. 109, pN.PAG-N.PAG. 1p.
Subjects: Static random access memory chips, On-chip charge pumps, Semiconductor technology
Abstract: This paper presents an on-chip 65-nm CMOS SRAM macro achieving ultra-low standby power through simultaneous source-line and body-line biasing control. The proposed architecture combines adaptive source-line regulation via a replica-cell-based feedback loop with stable body bias generation using an on-chip low-frequency charge pump. This dual-biasing approach effectively suppresses both NMOS and PMOS leakage components, overcoming the fundamental limitations of single-scheme techniques where only one type of leakage is addressed. Post-layout simulations demonstrate the standby leakage current of 0.45 μW/Mb at VDD = 1.5 V, representing a reduction of more than four orders of magnitude compared to conventional operation while maintaining sub-10 ns access times. The design employs standard 6T bitcells without area penalty, requiring only 6% area overhead including VPP generation circuits. All bias generation circuits are integrated on-chip, eliminating the need for external bias supplies. Comparative analysis with prior works confirms that the proposed macro achieves the lowest reported leakage among 65-nm SRAMs at nominal voltage. Unlike previous approaches requiring aggressive VDD scaling or larger cell architectures, this design maintains ultra-low leakage at standard operating voltage. The SRAM macro provides an immediately practical solution for battery-powered mobile and IoT applications where extended standby lifetime is critical. • Simultaneous source-line and body-line biasing for ultra-low SRAM leakage. • Achieves 0.45 μW/Mb at VDD = 1.5V with 6% overhead in 65-nm CMOS. • Replica-cell feedback adaptively sets source-line voltage across process corners for minimizing leakage. • On-chip charge pump with sub-kHz sensing minimizes standby power. • Best reported leakage number among 65-nm SRAMs at nominal voltage operation. [ABSTRACT FROM AUTHOR]
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Database: Engineering Source
Description
Abstract:This paper presents an on-chip 65-nm CMOS SRAM macro achieving ultra-low standby power through simultaneous source-line and body-line biasing control. The proposed architecture combines adaptive source-line regulation via a replica-cell-based feedback loop with stable body bias generation using an on-chip low-frequency charge pump. This dual-biasing approach effectively suppresses both NMOS and PMOS leakage components, overcoming the fundamental limitations of single-scheme techniques where only one type of leakage is addressed. Post-layout simulations demonstrate the standby leakage current of 0.45 μW/Mb at VDD = 1.5 V, representing a reduction of more than four orders of magnitude compared to conventional operation while maintaining sub-10 ns access times. The design employs standard 6T bitcells without area penalty, requiring only 6% area overhead including VPP generation circuits. All bias generation circuits are integrated on-chip, eliminating the need for external bias supplies. Comparative analysis with prior works confirms that the proposed macro achieves the lowest reported leakage among 65-nm SRAMs at nominal voltage. Unlike previous approaches requiring aggressive VDD scaling or larger cell architectures, this design maintains ultra-low leakage at standard operating voltage. The SRAM macro provides an immediately practical solution for battery-powered mobile and IoT applications where extended standby lifetime is critical. • Simultaneous source-line and body-line biasing for ultra-low SRAM leakage. • Achieves 0.45 μW/Mb at VDD = 1.5V with 6% overhead in 65-nm CMOS. • Replica-cell feedback adaptively sets source-line voltage across process corners for minimizing leakage. • On-chip charge pump with sub-kHz sensing minimizes standby power. • Best reported leakage number among 65-nm SRAMs at nominal voltage operation. [ABSTRACT FROM AUTHOR]
ISSN:01679260
DOI:10.1016/j.vlsi.2026.102698