On-chip SRAM macro with 0.45μW/Mbit-leakage data retention using simultaneous control of source-line and body-line biasing.
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| Title: | On-chip SRAM macro with 0.45μW/Mbit-leakage data retention using simultaneous control of source-line and body-line biasing. |
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| Authors: | Jo, Hyejin1 (AUTHOR), Lee, Jaesung1 (AUTHOR), Yun, Dai1 (AUTHOR), Mun, Jihwan1 (AUTHOR), Min, Kyeong-Sik1 (AUTHOR) mks@kookmin.ac.kr |
| Source: | Integration: The VLSI Journal. Jul2026, Vol. 109, pN.PAG-N.PAG. 1p. |
| Subjects: | Static random access memory chips, On-chip charge pumps, Semiconductor technology |
| Abstract: | This paper presents an on-chip 65-nm CMOS SRAM macro achieving ultra-low standby power through simultaneous source-line and body-line biasing control. The proposed architecture combines adaptive source-line regulation via a replica-cell-based feedback loop with stable body bias generation using an on-chip low-frequency charge pump. This dual-biasing approach effectively suppresses both NMOS and PMOS leakage components, overcoming the fundamental limitations of single-scheme techniques where only one type of leakage is addressed. Post-layout simulations demonstrate the standby leakage current of 0.45 μW/Mb at VDD = 1.5 V, representing a reduction of more than four orders of magnitude compared to conventional operation while maintaining sub-10 ns access times. The design employs standard 6T bitcells without area penalty, requiring only 6% area overhead including VPP generation circuits. All bias generation circuits are integrated on-chip, eliminating the need for external bias supplies. Comparative analysis with prior works confirms that the proposed macro achieves the lowest reported leakage among 65-nm SRAMs at nominal voltage. Unlike previous approaches requiring aggressive VDD scaling or larger cell architectures, this design maintains ultra-low leakage at standard operating voltage. The SRAM macro provides an immediately practical solution for battery-powered mobile and IoT applications where extended standby lifetime is critical. • Simultaneous source-line and body-line biasing for ultra-low SRAM leakage. • Achieves 0.45 μW/Mb at VDD = 1.5V with 6% overhead in 65-nm CMOS. • Replica-cell feedback adaptively sets source-line voltage across process corners for minimizing leakage. • On-chip charge pump with sub-kHz sensing minimizes standby power. • Best reported leakage number among 65-nm SRAMs at nominal voltage operation. [ABSTRACT FROM AUTHOR] |
| Copyright of Integration: The VLSI Journal is the property of Elsevier B.V. and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 194605728 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: On-chip SRAM macro with 0.45μW/Mbit-leakage data retention using simultaneous control of source-line and body-line biasing. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Jo%2C+Hyejin%22">Jo, Hyejin</searchLink><relatesTo>1</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Lee%2C+Jaesung%22">Lee, Jaesung</searchLink><relatesTo>1</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Yun%2C+Dai%22">Yun, Dai</searchLink><relatesTo>1</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Mun%2C+Jihwan%22">Mun, Jihwan</searchLink><relatesTo>1</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Min%2C+Kyeong-Sik%22">Min, Kyeong-Sik</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> mks@kookmin.ac.kr</i> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Integration%3A+The+VLSI+Journal%22">Integration: The VLSI Journal</searchLink>. Jul2026, Vol. 109, pN.PAG-N.PAG. 1p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Static+random+access+memory+chips%22">Static random access memory chips</searchLink><br /><searchLink fieldCode="DE" term="%22On-chip+charge+pumps%22">On-chip charge pumps</searchLink><br /><searchLink fieldCode="DE" term="%22Semiconductor+technology%22">Semiconductor technology</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: This paper presents an on-chip 65-nm CMOS SRAM macro achieving ultra-low standby power through simultaneous source-line and body-line biasing control. The proposed architecture combines adaptive source-line regulation via a replica-cell-based feedback loop with stable body bias generation using an on-chip low-frequency charge pump. This dual-biasing approach effectively suppresses both NMOS and PMOS leakage components, overcoming the fundamental limitations of single-scheme techniques where only one type of leakage is addressed. Post-layout simulations demonstrate the standby leakage current of 0.45 μW/Mb at VDD = 1.5 V, representing a reduction of more than four orders of magnitude compared to conventional operation while maintaining sub-10 ns access times. The design employs standard 6T bitcells without area penalty, requiring only 6% area overhead including VPP generation circuits. All bias generation circuits are integrated on-chip, eliminating the need for external bias supplies. Comparative analysis with prior works confirms that the proposed macro achieves the lowest reported leakage among 65-nm SRAMs at nominal voltage. Unlike previous approaches requiring aggressive VDD scaling or larger cell architectures, this design maintains ultra-low leakage at standard operating voltage. The SRAM macro provides an immediately practical solution for battery-powered mobile and IoT applications where extended standby lifetime is critical. • Simultaneous source-line and body-line biasing for ultra-low SRAM leakage. • Achieves 0.45 μW/Mb at VDD = 1.5V with 6% overhead in 65-nm CMOS. • Replica-cell feedback adaptively sets source-line voltage across process corners for minimizing leakage. • On-chip charge pump with sub-kHz sensing minimizes standby power. • Best reported leakage number among 65-nm SRAMs at nominal voltage operation. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of Integration: The VLSI Journal is the property of Elsevier B.V. and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1016/j.vlsi.2026.102698 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 1 StartPage: N.PAG Subjects: – SubjectFull: Static random access memory chips Type: general – SubjectFull: On-chip charge pumps Type: general – SubjectFull: Semiconductor technology Type: general Titles: – TitleFull: On-chip SRAM macro with 0.45μW/Mbit-leakage data retention using simultaneous control of source-line and body-line biasing. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Jo, Hyejin – PersonEntity: Name: NameFull: Lee, Jaesung – PersonEntity: Name: NameFull: Yun, Dai – PersonEntity: Name: NameFull: Mun, Jihwan – PersonEntity: Name: NameFull: Min, Kyeong-Sik IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 07 Text: Jul2026 Type: published Y: 2026 Identifiers: – Type: issn-print Value: 01679260 Numbering: – Type: volume Value: 109 Titles: – TitleFull: Integration: The VLSI Journal Type: main |
| ResultId | 1 |
