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A four MOSFETs based grounded memristor emulator.

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Bibliographic Details
Title:	A four MOSFETs based grounded memristor emulator.
Authors:	Kumar, Navnit¹ (AUTHOR) navnitnitmanipur@gmail.com, Pandey, Neeta² (AUTHOR) n66pandey@rediffmail.com, Kumar, Manjeet² (AUTHOR) manjeetchhillar@gmail.com, Kumar, Manish³ (AUTHOR) manishk19071984@gmail.com
Source:	Analog Integrated Circuits & Signal Processing. Jun2026, Vol. 127 Issue 3, p1-11. 11p.
Abstract:	A novel off- the-shelf Grounded Memristor Emulator (GME) based on four MOS transistors is reported in this brief. It consists of one PMOS and three NMOS transistors. The proposed emulator utilizes MOS capacitors instead of passive capacitors. Consequently, it can be stated that the circuit is exceedingly easy and appropriate for VLSI implementation. The fingerprint of memristor is represented by a pinched hysteresis loop thoroughly analyzed by SPICE simulator utilizing 180-nm CMOS technology with a bias voltage of ± 0.45 V. The designed circuit demonstrates non-linear behavior effectively up to 400. The suggested circuit consumes 9.03 of power. Moreover, area of the layout of the proposed circuit is 627.41 Further, the analysis of non-ideal conditions and post-layout simulations have been incorporated to illustrate the impact of parasitic components on the designed memristor emulator. In addition, the feasible practical applications are examined via the implementation of relaxation oscillator, which is suitable for biomedical and neuromorphic applications. [ABSTRACT FROM AUTHOR]
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Database:	Engineering Source

Description
Abstract:	A novel off- the-shelf Grounded Memristor Emulator (GME) based on four MOS transistors is reported in this brief. It consists of one PMOS and three NMOS transistors. The proposed emulator utilizes MOS capacitors instead of passive capacitors. Consequently, it can be stated that the circuit is exceedingly easy and appropriate for VLSI implementation. The fingerprint of memristor is represented by a pinched hysteresis loop thoroughly analyzed by SPICE simulator utilizing 180-nm CMOS technology with a bias voltage of ± 0.45 V. The designed circuit demonstrates non-linear behavior effectively up to 400. The suggested circuit consumes 9.03 of power. Moreover, area of the layout of the proposed circuit is 627.41 Further, the analysis of non-ideal conditions and post-layout simulations have been incorporated to illustrate the impact of parasitic components on the designed memristor emulator. In addition, the feasible practical applications are examined via the implementation of relaxation oscillator, which is suitable for biomedical and neuromorphic applications. [ABSTRACT FROM AUTHOR]
ISSN:	09251030
DOI:	10.1007/s10470-026-02602-5