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A mixed-signal CMOS VLSI implementation of a spiking echo-state neural network for energy-efficient temporal signal processing.

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Title: A mixed-signal CMOS VLSI implementation of a spiking echo-state neural network for energy-efficient temporal signal processing.
Authors: Nirmala, R.1 (AUTHOR) rnirmala843r@gmail.com, Murugesan, Malathi2 (AUTHOR) malathi@egspec.org, Duraisamy, Sasikala3 (AUTHOR) drdsasikala@gmail.com, Senthilkumar, V. M.4 (AUTHOR) senthilkumar.vm@ritchennai.edu.in
Source: Interactions (30050731). 6/23/2026, Vol. 247 Issue 1, p1-24. 24p.
Subjects: CMOS integrated circuits, Artificial neural networks, Speech perception, Time series analysis
Abstract: In this paper, a mixed-signal CMOS ultra-low power spiking echo-state neural network (ESN) VLSI chip has been designed and experimentally characterized for the very low-power temporal signal processing application of Speech Recognition and sensor time-series analysis. It is a hybrid architecture that integrates analog subthreshold neuron dynamics and synaptic integration with a digital control unit to implement programmable reservoir weights and a digital readout unit for classification and regression tasks. The chip was fabricated in 65 nm CMOS technology and had 128 spiking reservoir neurons, 16,384 programmable synapses with 50% random connectivity, and an on-chip digital readout. Real-time series benchmarks were used to experiment the neuron firing behavior, reservoir echo dynamics and end-to-end inference performance. The reservoir spectral radius can be tuned in the range of 0.6 to 1.2 with a global scaling current. The chip has 92% classification accuracy, with only on-chip computation, for the spoken digit dataset which contains 10 digits and 16 speakers, and is split between train and test set with 10-fold cross-validation. The total system power consumption is 230µW (1.8µW per neuron) which is 230nJ per inference over a 1ms window and 9pJ per synaptic operation (SOP). The robustness to process variations is confirmed by Monte Carlo simulations and temperature corner analysis from − 20 °C to 80 °C, and the measured PWM pulse-width standard deviation is 4.8%, which is very close to the simulation result of 4.2%. The results show the feasibility of combining the spiking reservoir computing with mixed-signal VLSI to realize energy-efficient on-edge temporal intelligence. To our knowledge, this is the first CMOS mixed-signal ESN chip that integrates on-chip digital readout with a programmable spectral-radius tuning and sub-µJ-per-inference energy efficiency, clearly differentiating it from all the previous analog spiking neural networks arrays and digital reservoir computing systems found in the literature. [ABSTRACT FROM AUTHOR]
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Database: Engineering Source
Description
Abstract:In this paper, a mixed-signal CMOS ultra-low power spiking echo-state neural network (ESN) VLSI chip has been designed and experimentally characterized for the very low-power temporal signal processing application of Speech Recognition and sensor time-series analysis. It is a hybrid architecture that integrates analog subthreshold neuron dynamics and synaptic integration with a digital control unit to implement programmable reservoir weights and a digital readout unit for classification and regression tasks. The chip was fabricated in 65 nm CMOS technology and had 128 spiking reservoir neurons, 16,384 programmable synapses with 50% random connectivity, and an on-chip digital readout. Real-time series benchmarks were used to experiment the neuron firing behavior, reservoir echo dynamics and end-to-end inference performance. The reservoir spectral radius can be tuned in the range of 0.6 to 1.2 with a global scaling current. The chip has 92% classification accuracy, with only on-chip computation, for the spoken digit dataset which contains 10 digits and 16 speakers, and is split between train and test set with 10-fold cross-validation. The total system power consumption is 230µW (1.8µW per neuron) which is 230nJ per inference over a 1ms window and 9pJ per synaptic operation (SOP). The robustness to process variations is confirmed by Monte Carlo simulations and temperature corner analysis from − 20 °C to 80 °C, and the measured PWM pulse-width standard deviation is 4.8%, which is very close to the simulation result of 4.2%. The results show the feasibility of combining the spiking reservoir computing with mixed-signal VLSI to realize energy-efficient on-edge temporal intelligence. To our knowledge, this is the first CMOS mixed-signal ESN chip that integrates on-chip digital readout with a programmable spectral-radius tuning and sub-µJ-per-inference energy efficiency, clearly differentiating it from all the previous analog spiking neural networks arrays and digital reservoir computing systems found in the literature. [ABSTRACT FROM AUTHOR]
ISSN:30050731
DOI:10.1007/s10751-026-02615-6