Bibliographic Details
| Title: |
Efficient VLSI Architectures of Huffman Encoder. |
| Authors: |
Basiri, M. Mohamed Asan1 (AUTHOR) asan@iiitk.ac.in |
| Source: |
Circuits, Systems & Signal Processing. Jul2026, Vol. 45 Issue 7, p5857-5883. 27p. |
| Subjects: |
Huffman codes, Encoding, Digital communications, CMOS integrated circuits, Very large scale circuit integration, Buffer storage (Computer science) |
| Abstract: |
Huffman encoders are the most widely used source encoders in the digital communication systems. This manuscript proposes two architectures of Huffman encoders. In the former case, the total area is reduced by using the proposed folded sorter and buffers instead of the memory storage. In the latter case, one encoding of length N or two encodings of length in parallel are performed by using the encoder of length N. Here, the throughput is increased by allowing two encodings in parallel. All the existing and proposed designs are synthesised using 45 nm CMOS technology using Cadence. Our proposed former design of length 8 achieves reduction in area as compared with the canonical encoder design. Similarly, our proposed later design of length 8 and 4 achieves improvement in throughput as compared to the canonical encoder design. [ABSTRACT FROM AUTHOR] |
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| Database: |
Engineering Source |
