Efficient VLSI Architectures of Huffman Encoder.
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| Title: | Efficient VLSI Architectures of Huffman Encoder. |
|---|---|
| Authors: | Basiri, M. Mohamed Asan1 (AUTHOR) asan@iiitk.ac.in |
| Source: | Circuits, Systems & Signal Processing. Jul2026, Vol. 45 Issue 7, p5857-5883. 27p. |
| Subjects: | Huffman codes, Encoding, Digital communications, CMOS integrated circuits, Very large scale circuit integration, Buffer storage (Computer science) |
| Abstract: | Huffman encoders are the most widely used source encoders in the digital communication systems. This manuscript proposes two architectures of Huffman encoders. In the former case, the total area is reduced by using the proposed folded sorter and buffers instead of the memory storage. In the latter case, one encoding of length N or two encodings of length in parallel are performed by using the encoder of length N. Here, the throughput is increased by allowing two encodings in parallel. All the existing and proposed designs are synthesised using 45 nm CMOS technology using Cadence. Our proposed former design of length 8 achieves reduction in area as compared with the canonical encoder design. Similarly, our proposed later design of length 8 and 4 achieves improvement in throughput as compared to the canonical encoder design. [ABSTRACT FROM AUTHOR] |
| Copyright of Circuits, Systems & Signal Processing is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 194867723 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Efficient VLSI Architectures of Huffman Encoder. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Basiri%2C+M%2E+Mohamed+Asan%22">Basiri, M. Mohamed Asan</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> asan@iiitk.ac.in</i> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Circuits%2C+Systems+%26+Signal+Processing%22">Circuits, Systems & Signal Processing</searchLink>. Jul2026, Vol. 45 Issue 7, p5857-5883. 27p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Huffman+codes%22">Huffman codes</searchLink><br /><searchLink fieldCode="DE" term="%22Encoding%22">Encoding</searchLink><br /><searchLink fieldCode="DE" term="%22Digital+communications%22">Digital communications</searchLink><br /><searchLink fieldCode="DE" term="%22CMOS+integrated+circuits%22">CMOS integrated circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Very+large+scale+circuit+integration%22">Very large scale circuit integration</searchLink><br /><searchLink fieldCode="DE" term="%22Buffer+storage+%28Computer+science%29%22">Buffer storage (Computer science)</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: Huffman encoders are the most widely used source encoders in the digital communication systems. This manuscript proposes two architectures of Huffman encoders. In the former case, the total area is reduced by using the proposed folded sorter and buffers instead of the memory storage. In the latter case, one encoding of length N or two encodings of length in parallel are performed by using the encoder of length N. Here, the throughput is increased by allowing two encodings in parallel. All the existing and proposed designs are synthesised using 45 nm CMOS technology using Cadence. Our proposed former design of length 8 achieves reduction in area as compared with the canonical encoder design. Similarly, our proposed later design of length 8 and 4 achieves improvement in throughput as compared to the canonical encoder design. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of Circuits, Systems & Signal Processing is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1007/s00034-025-03468-0 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 27 StartPage: 5857 Subjects: – SubjectFull: Huffman codes Type: general – SubjectFull: Encoding Type: general – SubjectFull: Digital communications Type: general – SubjectFull: CMOS integrated circuits Type: general – SubjectFull: Very large scale circuit integration Type: general – SubjectFull: Buffer storage (Computer science) Type: general Titles: – TitleFull: Efficient VLSI Architectures of Huffman Encoder. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Basiri, M. Mohamed Asan IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 07 Text: Jul2026 Type: published Y: 2026 Identifiers: – Type: issn-print Value: 0278081X Numbering: – Type: volume Value: 45 – Type: issue Value: 7 Titles: – TitleFull: Circuits, Systems & Signal Processing Type: main |
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