Elastic Fixed-Point Arithmetic-Logic Unit Based on Hybrid Adder And Vedic Mathematic.

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Bibliographic Details
Title:	Elastic Fixed-Point Arithmetic-Logic Unit Based on Hybrid Adder And Vedic Mathematic.
Authors:	GH. Ali, Fatima¹ pgs.fatimah.ali@uobasrah.edu.iq, Samir Almusali, Raqia², K. AL-Assfor, Fatemah¹
Source:	Iraqi Journal for Electrical & Electronic Engineering. Jun2026, Vol. 22 Issue 1, p299-310. 12p.
Subjects:	Complex numbers, Field programmable gate arrays, Mathematics, Digital signal processing
Abstract (English):	High speed and area reduction of the Arithmetic-Logic Unit (ALU) have a fundamental role in modern processors, especially in digital signal processor (DSP). In this paper, a new elastic fixed-point (Fx-P) ALU module is proposed to perform multiple operations on real and complex numbers. The arithmetic part of the ALU executes operations such as addition, subtraction, increment, decrement, and multiplication on real numbers. For complex operands, the proposed ALU executes three operations comprising addition, subtraction, complex conjugate of complex numbers. The logical part performs the basic operations including AND, OR, NAND, NOR, XOR, XNOR, NOT and BUFFER operations. The proposed design is based on utilizing an enhanced design of a hybrid adder consists of a Han Carlson adder with a carry-select adder (EHC-CSLA) and an improved design of the Vedic multiplier to achieve multiplication operation of real numbers. A 16-bit and a 32-bit EHC-CSLA are designed first to perform real/complex addition-and- subtraction on both data types. Then, an improved-Vedic multiplier (IVM) is designed to perform multiplication on two real operands. The proposed EHC-CSLAs, numerous bit-sizes of the IVMs, and the elastic design of real/ complex ALU modules in this work are coded in VHDL, simulated, and synthesized by Xilinx ISE14.7 tool on different FPGA families. The performance results demonstrate appreciable reductions in delay and area usage in comparison to the most counterpart multipliers and ALU designs. [ABSTRACT FROM AUTHOR]
Abstract (Arabic):	يركز المقال على تصميم وتنفيذ وحدة منطق حسابية (ALU) مرنة للنقطة الثابتة (Fx-P) قادرة على أداء العمليات الحسابية والمنطقية بكفاءة على الأعداد الحقيقية والمركبة على حد سواء. تدمج وحدة ALU المقترحة جامع جمع هجين معزز يُطلق عليه اسم EHC-CSLA (جامع هان-كارلسون المحسن مع اختيار الحمل)، والذي يجمع بين جامع هان-كارلسون وجامع اختيار الحمل، بالإضافة إلى مضاعف فيديك محسن (IVM) يعتمد على الرياضيات الفيدية لتحسين عملية ضرب الأعداد الحقيقية. تم تصميم الوحدة لدعم عرض بيانات 16 بت و32 بت، وتدعم عمليات حسابية متعددة تشمل الجمع والطرح والزيادة والنقصان والضرب للأعداد الحقيقية، بالإضافة إلى الجمع والطرح والترافق المركب للأعداد المركبة، إلى جانب الوظائف المنطقية الأساسية. بعد تركيبها ومحاكاتها على عائلات مختلفة من الـ FPGA، أظهر التصميم تقليصات كبيرة في التأخير واستهلاك المساحة مقارنة بالتصاميم الحالية لوحدات ALU والمضاعفات، حيث حقق تخفيضًا في التأخير يصل إلى 50% في بعض التكوينات. تسهم هذه الدراسة في تقديم بنية جديدة لوحدة ALU مرنة توازن بين السرعة العالية وكفاءة المساحة لتطبيقات معالجة الإشارات الرقمية التي تتعامل مع بيانات نقطة ثابتة حقيقية ومركبة. [Extracted from the article]
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Database:	Engineering Source

Description
Abstract:	High speed and area reduction of the Arithmetic-Logic Unit (ALU) have a fundamental role in modern processors, especially in digital signal processor (DSP). In this paper, a new elastic fixed-point (Fx-P) ALU module is proposed to perform multiple operations on real and complex numbers. The arithmetic part of the ALU executes operations such as addition, subtraction, increment, decrement, and multiplication on real numbers. For complex operands, the proposed ALU executes three operations comprising addition, subtraction, complex conjugate of complex numbers. The logical part performs the basic operations including AND, OR, NAND, NOR, XOR, XNOR, NOT and BUFFER operations. The proposed design is based on utilizing an enhanced design of a hybrid adder consists of a Han Carlson adder with a carry-select adder (EHC-CSLA) and an improved design of the Vedic multiplier to achieve multiplication operation of real numbers. A 16-bit and a 32-bit EHC-CSLA are designed first to perform real/complex addition-and- subtraction on both data types. Then, an improved-Vedic multiplier (IVM) is designed to perform multiplication on two real operands. The proposed EHC-CSLAs, numerous bit-sizes of the IVMs, and the elastic design of real/ complex ALU modules in this work are coded in VHDL, simulated, and synthesized by Xilinx ISE14.7 tool on different FPGA families. The performance results demonstrate appreciable reductions in delay and area usage in comparison to the most counterpart multipliers and ALU designs. [ABSTRACT FROM AUTHOR]
ISSN:	18145892
DOI:	10.37917/ijeee.22.1.28