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Low-Power Approximate Adder Design for Image Processing and K-Medians Clustering Applications.

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Title: Low-Power Approximate Adder Design for Image Processing and K-Medians Clustering Applications.
Authors: Gupta, Sanjiv Kumar1 (AUTHOR) sanjiv.2019rel04@mnnit.ac.in, Dhawan, Amit1 (AUTHOR) dhawan@mnnit.ac.in, Tiwari, Manish1 (AUTHOR) mtiwari@mnnit.ac.in, Jha, Sumit Kumar1 (AUTHOR) sumit-k@mnnit.ac.in
Source: IETE Journal of Research. Apr2026, Vol. 72 Issue 4, p902-915. 14p.
Subjects: Adders (Digital electronics), Image processing, Approximation algorithms, Clustering algorithms, Fault tolerance (Engineering), Electronic circuit design, Computer performance
Abstract: Approximate computing is increasingly adopted in error-tolerant applications to improve circuit efficiency by trading off a small amount of accuracy for significant power, area, and delay reductions. Among arithmetic units, adders are fundamental components in many digital systems, and their optimization is critical for achieving low-power and hardware-efficient designs. This paper proposes two 8-bit approximate adders based on probability-based carry manipulation, achieving a balance between hardware efficiency and accuracy. Furthermore, the 8-bit architecture is extended to higher-bit designs for broader applicability. The proposed approximate adder Design-2, with the lowest dissipation, achieves improvements of 42% in power, 36% in area, 40% in delay, and 77.9% in Power-Area-Delay Product (PADP) compared to the exact adder circuit. Both proposed approximate adders are also better than existing approximate designs in terms of overall hardware efficiency. The accuracy of the designs is assessed, and their practical effectiveness is demonstrated through two representative applications: image processing and K-medians clustering. Image processing performance is evaluated using Peak Signal-to-Noise Ratio (PSNR) and Structural Similarity Index Measure (SSIM). For K-medians clustering, the impact of approximation on clustering accuracy is evaluated using the Within-Cluster Sum of Absolute Distances (WSAD) metric. A Figure of Merit (FoM) is introduced to quantify trade-offs between efficiency and accuracy using performance, error, and image quality metrics. Results show that the proposed designs are better than existing adders and are suitable for error-resilient applications. [ABSTRACT FROM AUTHOR]
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Database: Engineering Source
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Abstract:Approximate computing is increasingly adopted in error-tolerant applications to improve circuit efficiency by trading off a small amount of accuracy for significant power, area, and delay reductions. Among arithmetic units, adders are fundamental components in many digital systems, and their optimization is critical for achieving low-power and hardware-efficient designs. This paper proposes two 8-bit approximate adders based on probability-based carry manipulation, achieving a balance between hardware efficiency and accuracy. Furthermore, the 8-bit architecture is extended to higher-bit designs for broader applicability. The proposed approximate adder Design-2, with the lowest dissipation, achieves improvements of 42% in power, 36% in area, 40% in delay, and 77.9% in Power-Area-Delay Product (PADP) compared to the exact adder circuit. Both proposed approximate adders are also better than existing approximate designs in terms of overall hardware efficiency. The accuracy of the designs is assessed, and their practical effectiveness is demonstrated through two representative applications: image processing and K-medians clustering. Image processing performance is evaluated using Peak Signal-to-Noise Ratio (PSNR) and Structural Similarity Index Measure (SSIM). For K-medians clustering, the impact of approximation on clustering accuracy is evaluated using the Within-Cluster Sum of Absolute Distances (WSAD) metric. A Figure of Merit (FoM) is introduced to quantify trade-offs between efficiency and accuracy using performance, error, and image quality metrics. Results show that the proposed designs are better than existing adders and are suitable for error-resilient applications. [ABSTRACT FROM AUTHOR]
ISSN:03772063
DOI:10.1080/03772063.2025.2592681