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Low-Power Approximate Adder Design for Image Processing and K-Medians Clustering Applications.

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Title: Low-Power Approximate Adder Design for Image Processing and K-Medians Clustering Applications.
Authors: Gupta, Sanjiv Kumar1 (AUTHOR) sanjiv.2019rel04@mnnit.ac.in, Dhawan, Amit1 (AUTHOR) dhawan@mnnit.ac.in, Tiwari, Manish1 (AUTHOR) mtiwari@mnnit.ac.in, Jha, Sumit Kumar1 (AUTHOR) sumit-k@mnnit.ac.in
Source: IETE Journal of Research. Apr2026, Vol. 72 Issue 4, p902-915. 14p.
Subjects: Adders (Digital electronics), Image processing, Approximation algorithms, Clustering algorithms, Fault tolerance (Engineering), Electronic circuit design, Computer performance
Abstract: Approximate computing is increasingly adopted in error-tolerant applications to improve circuit efficiency by trading off a small amount of accuracy for significant power, area, and delay reductions. Among arithmetic units, adders are fundamental components in many digital systems, and their optimization is critical for achieving low-power and hardware-efficient designs. This paper proposes two 8-bit approximate adders based on probability-based carry manipulation, achieving a balance between hardware efficiency and accuracy. Furthermore, the 8-bit architecture is extended to higher-bit designs for broader applicability. The proposed approximate adder Design-2, with the lowest dissipation, achieves improvements of 42% in power, 36% in area, 40% in delay, and 77.9% in Power-Area-Delay Product (PADP) compared to the exact adder circuit. Both proposed approximate adders are also better than existing approximate designs in terms of overall hardware efficiency. The accuracy of the designs is assessed, and their practical effectiveness is demonstrated through two representative applications: image processing and K-medians clustering. Image processing performance is evaluated using Peak Signal-to-Noise Ratio (PSNR) and Structural Similarity Index Measure (SSIM). For K-medians clustering, the impact of approximation on clustering accuracy is evaluated using the Within-Cluster Sum of Absolute Distances (WSAD) metric. A Figure of Merit (FoM) is introduced to quantify trade-offs between efficiency and accuracy using performance, error, and image quality metrics. Results show that the proposed designs are better than existing adders and are suitable for error-resilient applications. [ABSTRACT FROM AUTHOR]
Copyright of IETE Journal of Research is the property of Taylor & Francis Ltd and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
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DbLabel: Engineering Source
An: 194972680
AccessLevel: 6
PubType: Academic Journal
PubTypeId: academicJournal
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  Data: Low-Power Approximate Adder Design for Image Processing and K-Medians Clustering Applications.
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  Data: <searchLink fieldCode="AR" term="%22Gupta%2C+Sanjiv+Kumar%22">Gupta, Sanjiv Kumar</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> sanjiv.2019rel04@mnnit.ac.in</i><br /><searchLink fieldCode="AR" term="%22Dhawan%2C+Amit%22">Dhawan, Amit</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> dhawan@mnnit.ac.in</i><br /><searchLink fieldCode="AR" term="%22Tiwari%2C+Manish%22">Tiwari, Manish</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> mtiwari@mnnit.ac.in</i><br /><searchLink fieldCode="AR" term="%22Jha%2C+Sumit+Kumar%22">Jha, Sumit Kumar</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> sumit-k@mnnit.ac.in</i>
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  Data: <searchLink fieldCode="JN" term="%22IETE+Journal+of+Research%22">IETE Journal of Research</searchLink>. Apr2026, Vol. 72 Issue 4, p902-915. 14p.
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  Data: <searchLink fieldCode="DE" term="%22Adders+%28Digital+electronics%29%22">Adders (Digital electronics)</searchLink><br /><searchLink fieldCode="DE" term="%22Image+processing%22">Image processing</searchLink><br /><searchLink fieldCode="DE" term="%22Approximation+algorithms%22">Approximation algorithms</searchLink><br /><searchLink fieldCode="DE" term="%22Clustering+algorithms%22">Clustering algorithms</searchLink><br /><searchLink fieldCode="DE" term="%22Fault+tolerance+%28Engineering%29%22">Fault tolerance (Engineering)</searchLink><br /><searchLink fieldCode="DE" term="%22Electronic+circuit+design%22">Electronic circuit design</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+performance%22">Computer performance</searchLink>
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  Data: Approximate computing is increasingly adopted in error-tolerant applications to improve circuit efficiency by trading off a small amount of accuracy for significant power, area, and delay reductions. Among arithmetic units, adders are fundamental components in many digital systems, and their optimization is critical for achieving low-power and hardware-efficient designs. This paper proposes two 8-bit approximate adders based on probability-based carry manipulation, achieving a balance between hardware efficiency and accuracy. Furthermore, the 8-bit architecture is extended to higher-bit designs for broader applicability. The proposed approximate adder Design-2, with the lowest dissipation, achieves improvements of 42% in power, 36% in area, 40% in delay, and 77.9% in Power-Area-Delay Product (PADP) compared to the exact adder circuit. Both proposed approximate adders are also better than existing approximate designs in terms of overall hardware efficiency. The accuracy of the designs is assessed, and their practical effectiveness is demonstrated through two representative applications: image processing and K-medians clustering. Image processing performance is evaluated using Peak Signal-to-Noise Ratio (PSNR) and Structural Similarity Index Measure (SSIM). For K-medians clustering, the impact of approximation on clustering accuracy is evaluated using the Within-Cluster Sum of Absolute Distances (WSAD) metric. A Figure of Merit (FoM) is introduced to quantify trade-offs between efficiency and accuracy using performance, error, and image quality metrics. Results show that the proposed designs are better than existing adders and are suitable for error-resilient applications. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of IETE Journal of Research is the property of Taylor & Francis Ltd and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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RecordInfo BibRecord:
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      – Type: doi
        Value: 10.1080/03772063.2025.2592681
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      – Code: eng
        Text: English
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        PageCount: 14
        StartPage: 902
    Subjects:
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        Type: general
      – SubjectFull: Image processing
        Type: general
      – SubjectFull: Approximation algorithms
        Type: general
      – SubjectFull: Clustering algorithms
        Type: general
      – SubjectFull: Fault tolerance (Engineering)
        Type: general
      – SubjectFull: Electronic circuit design
        Type: general
      – SubjectFull: Computer performance
        Type: general
    Titles:
      – TitleFull: Low-Power Approximate Adder Design for Image Processing and K-Medians Clustering Applications.
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            NameFull: Gupta, Sanjiv Kumar
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            NameFull: Dhawan, Amit
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            NameFull: Tiwari, Manish
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            – D: 01
              M: 04
              Text: Apr2026
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              Y: 2026
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