EFFICIENT SHARED-MULTIPLIER MIXED-RADIX FFT ARCHITECTURE WITH DYNAMIC RESOURCE SCHEDULING FOR ULTRA-HIGH-SPEED OFDM SYSTEMS.

Saved in:

Bibliographic Details
Title:	EFFICIENT SHARED-MULTIPLIER MIXED-RADIX FFT ARCHITECTURE WITH DYNAMIC RESOURCE SCHEDULING FOR ULTRA-HIGH-SPEED OFDM SYSTEMS.
Authors:	VEJENDLA, NANCHARAIAH¹, REDDY, R. RAMANA², BALAJI, N.³
Source:	i-Manager's Journal on Electrical Engineering. Mar2026, Vol. 19 Issue 3, p1-15. 15p.
Subjects:	Fast Fourier transforms, Orthogonal frequency division multiplexing, Field programmable gate arrays, Resource allocation, Digital signal processing
Abstract:	This paper presents an enhanced shared-multiplier scheduling scheme (e-SMSS) for ultra-high-speed Fast Fourier Transform (FFT) and Inverse FFT (IFFT) processors targeting next-generation optical and millimeter-wave OFDM standards. Building upon the mixed-radix multipath delay commutator (MRMDC) framework, the proposed architecture introduces dynamic twiddle-factor sharing and pipelined multiplier reuse across stages, reducing the complex multiplier count by 36% compared to prior works while supporting 128/256/512/1024-point transforms. The design employs eight parallel data paths with reconfigurable butterfly units and a multicycle scheduling controller that orchestrates multiplier access without throughput loss. The proposed design was synthesized using Xilinx Vivado on Veterx-7 FPGA, the processor achieves a 40 GS/s throughput at 500 MHz. Synthesizable Verilog models for the core butterfly, shared multiplier array, and scheduling controller were provided and validated. [ABSTRACT FROM AUTHOR]
	Copyright of i-Manager's Journal on Electrical Engineering is the property of i-manager Publications and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database:	Engineering Source

Description
Abstract:	This paper presents an enhanced shared-multiplier scheduling scheme (e-SMSS) for ultra-high-speed Fast Fourier Transform (FFT) and Inverse FFT (IFFT) processors targeting next-generation optical and millimeter-wave OFDM standards. Building upon the mixed-radix multipath delay commutator (MRMDC) framework, the proposed architecture introduces dynamic twiddle-factor sharing and pipelined multiplier reuse across stages, reducing the complex multiplier count by 36% compared to prior works while supporting 128/256/512/1024-point transforms. The design employs eight parallel data paths with reconfigurable butterfly units and a multicycle scheduling controller that orchestrates multiplier access without throughput loss. The proposed design was synthesized using Xilinx Vivado on Veterx-7 FPGA, the processor achieves a 40 GS/s throughput at 500 MHz. Synthesizable Verilog models for the core butterfly, shared multiplier array, and scheduling controller were provided and validated. [ABSTRACT FROM AUTHOR]
ISSN:	09738835
DOI:	10.26634/jee.19.3.1119