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HARLD: A RISC-V Based Tightly Coupled Heterogeneous Computing Architecture for Low-Density Parity Check Decoding.

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Title: HARLD: A RISC-V Based Tightly Coupled Heterogeneous Computing Architecture for Low-Density Parity Check Decoding.
Authors: Wang, Bing1 (AUTHOR) wangbing@chinamobile.com, Ma, Zi-Rui2,3 (AUTHOR) mazirui24s@ict.ac.cn, Wu, Hai-Bin2 (AUTHOR) wuhaibin@ict.ac.cn, Zhang, Fu-Lin2,3 (AUTHOR) zhangfulin24s@ict.ac.cn, Wang, Yue2,3 (AUTHOR) wangyue24s@ict.ac.cn, Fan, Zhi-Hua2,3 (AUTHOR) fanzhihua@ict.ac.cn, Li, Wen-Ming2,3 (AUTHOR) liwenming@ict.ac.cn, Ye, Xiao-Chun2,3 (AUTHOR) yexiaochun@ict.ac.cn, Fan, Dong-Rui2,3 (AUTHOR) fandr@ict.ac.cn
Source: Journal of Computer Science & Technology (10009000). Mar2026, Vol. 41 Issue 2, p774-790. 17p.
Subjects: Low density parity check codes, Heterogeneous computing, Channel coding, Energy consumption, 5G networks, Reduced instruction set computers, Computer architecture
Abstract: Low-density parity check (LDPC) decoding is an efficient error correction method in communication systems, especially in 5G networks, which require high performance and low latency; while common generalpurpose architectures cannot meet the requirements. There has been some research on accelerating LDPC decoding, but the current methods still suffer from limitations in performance, flexibility, and communication cost. In this paper, we propose HARLD (Heterogeneous Architecture of RISC-V for LDPC Decoding), a tightly coupled heterogeneous computing architecture based on extended RISC-V for LDPC decoding, consisting of a CPU and a processing array. Compared with a loosely coupled System-on-Chip (SoC)-bus baseline, the tightly coupled design improves throughput by up to 32.4% and reduces average latency by up to 24.7% across evaluated configurations, while also enhancing resource and energy efficiency: processing element utilization up to 93.5%, instruction RAM utilization increased by up to 4.8x, and energy efficiency improved by up to 24.8%. At the system level, area and power are reduced by 17.6% and 10.2%, respectively, versus the loosely coupled design. [ABSTRACT FROM AUTHOR]
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Database: Engineering Source
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Abstract:Low-density parity check (LDPC) decoding is an efficient error correction method in communication systems, especially in 5G networks, which require high performance and low latency; while common generalpurpose architectures cannot meet the requirements. There has been some research on accelerating LDPC decoding, but the current methods still suffer from limitations in performance, flexibility, and communication cost. In this paper, we propose HARLD (Heterogeneous Architecture of RISC-V for LDPC Decoding), a tightly coupled heterogeneous computing architecture based on extended RISC-V for LDPC decoding, consisting of a CPU and a processing array. Compared with a loosely coupled System-on-Chip (SoC)-bus baseline, the tightly coupled design improves throughput by up to 32.4% and reduces average latency by up to 24.7% across evaluated configurations, while also enhancing resource and energy efficiency: processing element utilization up to 93.5%, instruction RAM utilization increased by up to 4.8x, and energy efficiency improved by up to 24.8%. At the system level, area and power are reduced by 17.6% and 10.2%, respectively, versus the loosely coupled design. [ABSTRACT FROM AUTHOR]
ISSN:10009000
DOI:10.1007/s11390-025-5052-5