View in EDS

Design of High-Performance Low-Power Adder Circuits, 2 to 4 Decoder and 2 × 1 Mux Using RLG for VLSI Applications.

Saved in:
Bibliographic Details
Title: Design of High-Performance Low-Power Adder Circuits, 2 to 4 Decoder and 2 × 1 Mux Using RLG for VLSI Applications.
Authors: Syed, Zahiruddin1 (AUTHOR) zaheer.usk@gmail.com, Subbarayudu, P.2 (AUTHOR), Krishna, P. V. S. Murali3 (AUTHOR), Bhasha, A. Valli1 (AUTHOR), Reddy, P. Dileep Kumar1 (AUTHOR)
Source: Russian Microelectronics. Apr2026, Vol. 55 Issue 2, p369-375. 7p.
Subjects: Reversible computing, Energy consumption, Application-specific integrated circuits, Computer logic
Abstract: This manuscript presents the implementation and analysis of arithmetic and logic circuits, specifically adder circuits, 2 to 4 decoder, and 2 × 1 multiplexer using reversible logic gates (RLGs). RLGs have garnered significant interest in VLSI design due to their inherent capabilities, like minimal power consumption and reduced thermal output, making them best suited for energy-conserving computational systems. Experimental evaluations reveal that the proposed half adder design consumes merely 16.40 μW with a propagation delay of 5.04 ps, while the full adder implementation requires 22.67 μW and exhibits a delay of 10.48 ps. Additionally, the 2 to 4 decoder achieved 1 μW power consumption with a 1000 ps delay, and the 2 × 1 multiplexer registered 5.05 μW power usage with a 435.7 ps delay. These metrics demonstrate substantial improvements in both operational speed and energy efficiency when compared to conventional gate based implementations. [ABSTRACT FROM AUTHOR]
Copyright of Russian Microelectronics is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
Description
Abstract:This manuscript presents the implementation and analysis of arithmetic and logic circuits, specifically adder circuits, 2 to 4 decoder, and 2 × 1 multiplexer using reversible logic gates (RLGs). RLGs have garnered significant interest in VLSI design due to their inherent capabilities, like minimal power consumption and reduced thermal output, making them best suited for energy-conserving computational systems. Experimental evaluations reveal that the proposed half adder design consumes merely 16.40 μW with a propagation delay of 5.04 ps, while the full adder implementation requires 22.67 μW and exhibits a delay of 10.48 ps. Additionally, the 2 to 4 decoder achieved 1 μW power consumption with a 1000 ps delay, and the 2 × 1 multiplexer registered 5.05 μW power usage with a 435.7 ps delay. These metrics demonstrate substantial improvements in both operational speed and energy efficiency when compared to conventional gate based implementations. [ABSTRACT FROM AUTHOR]
ISSN:10637397
DOI:10.1134/S1063739726600056