Bibliographic Details
| Title: |
A FPGA-Based Systolic Array Prototype Implementing the Quadrant Interlocking Factorization Method. |
| Authors: |
Karra, M.1 mkarra@ee.duth.gr, Bekakos, M.1 mbekakos@ee.duth.gr |
| Source: |
Journal of Supercomputing. Sep2006, Vol. 37 Issue 3, p319-331. 13p. 1 Color Photograph, 8 Diagrams, 2 Charts. |
| Subjects: |
Systolic array circuits, Very large scale circuit integration, Field programmable gate arrays, Integrated circuits, Very high speed integrated circuits, Programmable logic devices, Gate array circuits, Factorization of operators, Prototypes |
| Abstract: |
The systolic processing offers the possibility of solving a large number of standard problems on multicellular computing devices with autonomous cells (Processing Elements—PEs). The resulting systolic arrays exploit the underlying parallelism of many computationally intensive problems and offer a vital and effective way of handling them. Advances in technology and especially in VLSI and FPGA have an ongoing contribution to the evolution of systolic arrays. Herein, a FPGA-based Systolic array prototype implementing the Factorization stage of the Quadrant Interlocking Factorization—QIF (Butterfly) method is presented and the corresponding time-complexities achieved are discussed. [ABSTRACT FROM AUTHOR] |
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| Database: |
Engineering Source |
