A FPGA-Based Systolic Array Prototype Implementing the Quadrant Interlocking Factorization Method.
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| Title: | A FPGA-Based Systolic Array Prototype Implementing the Quadrant Interlocking Factorization Method. |
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| Authors: | Karra, M.1 mkarra@ee.duth.gr, Bekakos, M.1 mbekakos@ee.duth.gr |
| Source: | Journal of Supercomputing. Sep2006, Vol. 37 Issue 3, p319-331. 13p. 1 Color Photograph, 8 Diagrams, 2 Charts. |
| Subjects: | Systolic array circuits, Very large scale circuit integration, Field programmable gate arrays, Integrated circuits, Very high speed integrated circuits, Programmable logic devices, Gate array circuits, Factorization of operators, Prototypes |
| Abstract: | The systolic processing offers the possibility of solving a large number of standard problems on multicellular computing devices with autonomous cells (Processing Elements—PEs). The resulting systolic arrays exploit the underlying parallelism of many computationally intensive problems and offer a vital and effective way of handling them. Advances in technology and especially in VLSI and FPGA have an ongoing contribution to the evolution of systolic arrays. Herein, a FPGA-based Systolic array prototype implementing the Factorization stage of the Quadrant Interlocking Factorization—QIF (Butterfly) method is presented and the corresponding time-complexities achieved are discussed. [ABSTRACT FROM AUTHOR] |
| Copyright of Journal of Supercomputing is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
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| Header | DbId: egs DbLabel: Engineering Source An: 22164742 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: A FPGA-Based Systolic Array Prototype Implementing the Quadrant Interlocking Factorization Method. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Karra%2C+M%2E%22">Karra, M.</searchLink><relatesTo>1</relatesTo><i> mkarra@ee.duth.gr</i><br /><searchLink fieldCode="AR" term="%22Bekakos%2C+M%2E%22">Bekakos, M.</searchLink><relatesTo>1</relatesTo><i> mbekakos@ee.duth.gr</i> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Journal+of+Supercomputing%22">Journal of Supercomputing</searchLink>. Sep2006, Vol. 37 Issue 3, p319-331. 13p. 1 Color Photograph, 8 Diagrams, 2 Charts. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Systolic+array+circuits%22">Systolic array circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Very+large+scale+circuit+integration%22">Very large scale circuit integration</searchLink><br /><searchLink fieldCode="DE" term="%22Field+programmable+gate+arrays%22">Field programmable gate arrays</searchLink><br /><searchLink fieldCode="DE" term="%22Integrated+circuits%22">Integrated circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Very+high+speed+integrated+circuits%22">Very high speed integrated circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Programmable+logic+devices%22">Programmable logic devices</searchLink><br /><searchLink fieldCode="DE" term="%22Gate+array+circuits%22">Gate array circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Factorization+of+operators%22">Factorization of operators</searchLink><br /><searchLink fieldCode="DE" term="%22Prototypes%22">Prototypes</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: The systolic processing offers the possibility of solving a large number of standard problems on multicellular computing devices with autonomous cells (Processing Elements—PEs). The resulting systolic arrays exploit the underlying parallelism of many computationally intensive problems and offer a vital and effective way of handling them. Advances in technology and especially in VLSI and FPGA have an ongoing contribution to the evolution of systolic arrays. Herein, a FPGA-based Systolic array prototype implementing the Factorization stage of the Quadrant Interlocking Factorization—QIF (Butterfly) method is presented and the corresponding time-complexities achieved are discussed. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of Journal of Supercomputing is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1007/s11227-006-6633-x Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 13 StartPage: 319 Subjects: – SubjectFull: Systolic array circuits Type: general – SubjectFull: Very large scale circuit integration Type: general – SubjectFull: Field programmable gate arrays Type: general – SubjectFull: Integrated circuits Type: general – SubjectFull: Very high speed integrated circuits Type: general – SubjectFull: Programmable logic devices Type: general – SubjectFull: Gate array circuits Type: general – SubjectFull: Factorization of operators Type: general – SubjectFull: Prototypes Type: general Titles: – TitleFull: A FPGA-Based Systolic Array Prototype Implementing the Quadrant Interlocking Factorization Method. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Karra, M. – PersonEntity: Name: NameFull: Bekakos, M. IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 09 Text: Sep2006 Type: published Y: 2006 Identifiers: – Type: issn-print Value: 09208542 Numbering: – Type: volume Value: 37 – Type: issue Value: 3 Titles: – TitleFull: Journal of Supercomputing Type: main |
| ResultId | 1 |
