Parametric minimum hardware QR-factoriser architecture for V-BLAST detection.

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Bibliographic Details
Title:	Parametric minimum hardware QR-factoriser architecture for V-BLAST detection.
Authors:	Sobhanmanesh, F.¹, Nooshabadi, S.¹ saeid@unsw.edu.au
Source:	IEE Proceedings -- Circuits, Devices & Systems. Oct2006, Vol. 153 Issue 5, p433-441. 9p. 9 Diagrams, 6 Charts, 6 Graphs.
Subjects:	Wireless communications, Systolic array circuits, Transmitting antennas, Signal processing, Array processors, Critical path analysis, Least squares
Abstract:	The authors introduce a new architecture for the core processor for a V-BLAST detector. This architecture uses only two low complexity CORDIC processors for QR factorisation. The parameterised feature of the controller and address generator blocks provides a scalable architecture for the implementation of QR factorisation for a square matrix of any dimension. The reduced hardware complexity of the processors and its simple parameterised controller are two outstanding features of the architecture, resulting in a more suitable alternative architecture for QR factorisation than triangular systolic arrays. A comprehensive analysis of parameters influencing the hardware implementation and their effects on the error performance of the V-BLAST detector has been presented. The implementation of the proposed architecture on an Altera Stratix FPGA device results in a very small critical path delay. This provides a platform for the fast matrix triangularisation for applications requiring high data rates such as MIMO V-BLAST detectors. The maximum throughput values of up to 367 Mbit/s are reachable using this novel QR-factorisation architecture for the V-BLAST detector. [ABSTRACT FROM AUTHOR]
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Database:	Engineering Source

Description
Abstract:	The authors introduce a new architecture for the core processor for a V-BLAST detector. This architecture uses only two low complexity CORDIC processors for QR factorisation. The parameterised feature of the controller and address generator blocks provides a scalable architecture for the implementation of QR factorisation for a square matrix of any dimension. The reduced hardware complexity of the processors and its simple parameterised controller are two outstanding features of the architecture, resulting in a more suitable alternative architecture for QR factorisation than triangular systolic arrays. A comprehensive analysis of parameters influencing the hardware implementation and their effects on the error performance of the V-BLAST detector has been presented. The implementation of the proposed architecture on an Altera Stratix FPGA device results in a very small critical path delay. This provides a platform for the fast matrix triangularisation for applications requiring high data rates such as MIMO V-BLAST detectors. The maximum throughput values of up to 367 Mbit/s are reachable using this novel QR-factorisation architecture for the V-BLAST detector. [ABSTRACT FROM AUTHOR]
ISSN:	13502409
DOI:	10.1049/ip-cds:20060060