Parametric minimum hardware QR-factoriser architecture for V-BLAST detection.
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| Title: | Parametric minimum hardware QR-factoriser architecture for V-BLAST detection. |
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| Authors: | Sobhanmanesh, F.1, Nooshabadi, S.1 saeid@unsw.edu.au |
| Source: | IEE Proceedings -- Circuits, Devices & Systems. Oct2006, Vol. 153 Issue 5, p433-441. 9p. 9 Diagrams, 6 Charts, 6 Graphs. |
| Subjects: | Wireless communications, Systolic array circuits, Transmitting antennas, Signal processing, Array processors, Critical path analysis, Least squares |
| Abstract: | The authors introduce a new architecture for the core processor for a V-BLAST detector. This architecture uses only two low complexity CORDIC processors for QR factorisation. The parameterised feature of the controller and address generator blocks provides a scalable architecture for the implementation of QR factorisation for a square matrix of any dimension. The reduced hardware complexity of the processors and its simple parameterised controller are two outstanding features of the architecture, resulting in a more suitable alternative architecture for QR factorisation than triangular systolic arrays. A comprehensive analysis of parameters influencing the hardware implementation and their effects on the error performance of the V-BLAST detector has been presented. The implementation of the proposed architecture on an Altera Stratix FPGA device results in a very small critical path delay. This provides a platform for the fast matrix triangularisation for applications requiring high data rates such as MIMO V-BLAST detectors. The maximum throughput values of up to 367 Mbit/s are reachable using this novel QR-factorisation architecture for the V-BLAST detector. [ABSTRACT FROM AUTHOR] |
| Copyright of IEE Proceedings -- Circuits, Devices & Systems is the property of Institution of Engineering & Technology and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
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| Header | DbId: egs DbLabel: Engineering Source An: 22891646 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Parametric minimum hardware QR-factoriser architecture for V-BLAST detection. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Sobhanmanesh%2C+F%2E%22">Sobhanmanesh, F.</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Nooshabadi%2C+S%2E%22">Nooshabadi, S.</searchLink><relatesTo>1</relatesTo><i> saeid@unsw.edu.au</i> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22IEE+Proceedings+--+Circuits%2C+Devices+%26+Systems%22">IEE Proceedings -- Circuits, Devices & Systems</searchLink>. Oct2006, Vol. 153 Issue 5, p433-441. 9p. 9 Diagrams, 6 Charts, 6 Graphs. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Wireless+communications%22">Wireless communications</searchLink><br /><searchLink fieldCode="DE" term="%22Systolic+array+circuits%22">Systolic array circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Transmitting+antennas%22">Transmitting antennas</searchLink><br /><searchLink fieldCode="DE" term="%22Signal+processing%22">Signal processing</searchLink><br /><searchLink fieldCode="DE" term="%22Array+processors%22">Array processors</searchLink><br /><searchLink fieldCode="DE" term="%22Critical+path+analysis%22">Critical path analysis</searchLink><br /><searchLink fieldCode="DE" term="%22Least+squares%22">Least squares</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: The authors introduce a new architecture for the core processor for a V-BLAST detector. This architecture uses only two low complexity CORDIC processors for QR factorisation. The parameterised feature of the controller and address generator blocks provides a scalable architecture for the implementation of QR factorisation for a square matrix of any dimension. The reduced hardware complexity of the processors and its simple parameterised controller are two outstanding features of the architecture, resulting in a more suitable alternative architecture for QR factorisation than triangular systolic arrays. A comprehensive analysis of parameters influencing the hardware implementation and their effects on the error performance of the V-BLAST detector has been presented. The implementation of the proposed architecture on an Altera Stratix FPGA device results in a very small critical path delay. This provides a platform for the fast matrix triangularisation for applications requiring high data rates such as MIMO V-BLAST detectors. The maximum throughput values of up to 367 Mbit/s are reachable using this novel QR-factorisation architecture for the V-BLAST detector. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of IEE Proceedings -- Circuits, Devices & Systems is the property of Institution of Engineering & Technology and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1049/ip-cds:20060060 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 9 StartPage: 433 Subjects: – SubjectFull: Wireless communications Type: general – SubjectFull: Systolic array circuits Type: general – SubjectFull: Transmitting antennas Type: general – SubjectFull: Signal processing Type: general – SubjectFull: Array processors Type: general – SubjectFull: Critical path analysis Type: general – SubjectFull: Least squares Type: general Titles: – TitleFull: Parametric minimum hardware QR-factoriser architecture for V-BLAST detection. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Sobhanmanesh, F. – PersonEntity: Name: NameFull: Nooshabadi, S. IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 10 Text: Oct2006 Type: published Y: 2006 Identifiers: – Type: issn-print Value: 13502409 Numbering: – Type: volume Value: 153 – Type: issue Value: 5 Titles: – TitleFull: IEE Proceedings -- Circuits, Devices & Systems Type: main |
| ResultId | 1 |
