Computing all-pairs shortest paths on a linear systolic array and hardware realization on a reprogrammable FPGA platform.

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Bibliographic Details
Title:	Computing all-pairs shortest paths on a linear systolic array and hardware realization on a reprogrammable FPGA platform.
Authors:	Milovanović, E.¹ ema@elfak.ni.ac.yu, Milovanović, I.¹ igor@elfak.ni.ac.yu, Bekakos, M.² mbekakos@ee.duth.gr, Tselepis, I.² itselepi@ee.duth.gr
Source:	Journal of Supercomputing. Apr2007, Vol. 40 Issue 1, p49-66. 18p. 6 Diagrams, 6 Charts, 3 Graphs.
Subjects:	Systolic array circuits, Directed graphs, Computer simulation, Linear electric circuits, Algorithms, Vector processing (Computer science), Computer software, Computer engineering, Computer science
Abstract:	In this paper a regular bidirectional linear systolic array (RBLSA) for computing all-pairs shortest paths of a given directed graph is designed. The obtained array is optimal with respect to a number of processing elements (PE) for a given problem size. The execution time of the array has been minimized. To obtain RBLSA with optimal number of PEs, the accommodation of the inner computation space of the systolic algorithm to the projection direction vector is performed. Finally, FPGA-based reprogrammable systems are revolutionizing certain types of computation and digital logic, since as logic emulation systems they offer some orders of magnitude speedup over software simulation; herein, a FPGA realization of the RBLSA is investigated and the performance evaluation results are discussed. [ABSTRACT FROM AUTHOR]
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Database:	Engineering Source

Description
Abstract:	In this paper a regular bidirectional linear systolic array (RBLSA) for computing all-pairs shortest paths of a given directed graph is designed. The obtained array is optimal with respect to a number of processing elements (PE) for a given problem size. The execution time of the array has been minimized. To obtain RBLSA with optimal number of PEs, the accommodation of the inner computation space of the systolic algorithm to the projection direction vector is performed. Finally, FPGA-based reprogrammable systems are revolutionizing certain types of computation and digital logic, since as logic emulation systems they offer some orders of magnitude speedup over software simulation; herein, a FPGA realization of the RBLSA is investigated and the performance evaluation results are discussed. [ABSTRACT FROM AUTHOR]
ISSN:	09208542
DOI:	10.1007/s11227-006-0013-4