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Computing all-pairs shortest paths on a linear systolic array and hardware realization on a reprogrammable FPGA platform.

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Title: Computing all-pairs shortest paths on a linear systolic array and hardware realization on a reprogrammable FPGA platform.
Authors: Milovanović, E.1 ema@elfak.ni.ac.yu, Milovanović, I.1 igor@elfak.ni.ac.yu, Bekakos, M.2 mbekakos@ee.duth.gr, Tselepis, I.2 itselepi@ee.duth.gr
Source: Journal of Supercomputing. Apr2007, Vol. 40 Issue 1, p49-66. 18p. 6 Diagrams, 6 Charts, 3 Graphs.
Subjects: Systolic array circuits, Directed graphs, Computer simulation, Linear electric circuits, Algorithms, Vector processing (Computer science), Computer software, Computer engineering, Computer science
Abstract: In this paper a regular bidirectional linear systolic array (RBLSA) for computing all-pairs shortest paths of a given directed graph is designed. The obtained array is optimal with respect to a number of processing elements (PE) for a given problem size. The execution time of the array has been minimized. To obtain RBLSA with optimal number of PEs, the accommodation of the inner computation space of the systolic algorithm to the projection direction vector is performed. Finally, FPGA-based reprogrammable systems are revolutionizing certain types of computation and digital logic, since as logic emulation systems they offer some orders of magnitude speedup over software simulation; herein, a FPGA realization of the RBLSA is investigated and the performance evaluation results are discussed. [ABSTRACT FROM AUTHOR]
Copyright of Journal of Supercomputing is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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  Data: Computing all-pairs shortest paths on a linear systolic array and hardware realization on a reprogrammable FPGA platform.
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  Data: <searchLink fieldCode="AR" term="%22Milovanović%2C+E%2E%22">Milovanović, E.</searchLink><relatesTo>1</relatesTo><i> ema@elfak.ni.ac.yu</i><br /><searchLink fieldCode="AR" term="%22Milovanović%2C+I%2E%22">Milovanović, I.</searchLink><relatesTo>1</relatesTo><i> igor@elfak.ni.ac.yu</i><br /><searchLink fieldCode="AR" term="%22Bekakos%2C+M%2E%22">Bekakos, M.</searchLink><relatesTo>2</relatesTo><i> mbekakos@ee.duth.gr</i><br /><searchLink fieldCode="AR" term="%22Tselepis%2C+I%2E%22">Tselepis, I.</searchLink><relatesTo>2</relatesTo><i> itselepi@ee.duth.gr</i>
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  Data: <searchLink fieldCode="JN" term="%22Journal+of+Supercomputing%22">Journal of Supercomputing</searchLink>. Apr2007, Vol. 40 Issue 1, p49-66. 18p. 6 Diagrams, 6 Charts, 3 Graphs.
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  Data: <searchLink fieldCode="DE" term="%22Systolic+array+circuits%22">Systolic array circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Directed+graphs%22">Directed graphs</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+simulation%22">Computer simulation</searchLink><br /><searchLink fieldCode="DE" term="%22Linear+electric+circuits%22">Linear electric circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Algorithms%22">Algorithms</searchLink><br /><searchLink fieldCode="DE" term="%22Vector+processing+%28Computer+science%29%22">Vector processing (Computer science)</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+software%22">Computer software</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+engineering%22">Computer engineering</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+science%22">Computer science</searchLink>
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  Data: In this paper a regular bidirectional linear systolic array (RBLSA) for computing all-pairs shortest paths of a given directed graph is designed. The obtained array is optimal with respect to a number of processing elements (PE) for a given problem size. The execution time of the array has been minimized. To obtain RBLSA with optimal number of PEs, the accommodation of the inner computation space of the systolic algorithm to the projection direction vector is performed. Finally, FPGA-based reprogrammable systems are revolutionizing certain types of computation and digital logic, since as logic emulation systems they offer some orders of magnitude speedup over software simulation; herein, a FPGA realization of the RBLSA is investigated and the performance evaluation results are discussed. [ABSTRACT FROM AUTHOR]
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  Data: <i>Copyright of Journal of Supercomputing is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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              Text: Apr2007
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