Design Considerations for Scalable High-Performance Vision Systems Embedded in Industrial Print Inspection Machines.

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Bibliographic Details
Title:	Design Considerations for Scalable High-Performance Vision Systems Embedded in Industrial Print Inspection Machines.
Authors:	Fürtler, Johannes¹, Rössler, Peter², Brodersen, Jörg¹, Nachtnebel, Herbert³, Mayer, Konrad J.¹, Cadek, Gerhard⁴, Eckel, Christian⁴
Source:	EURASIP Journal on Embedded Systems. 2007 Special Issue 2, p1-10. 10p. 8 Diagrams, 2 Charts.
Subjects:	Embedded computer systems, Optical quality control, Field programmable gate arrays, Signal processing, Algorithms
Abstract:	This paper describes the design of a scalable high-performance vision system which is used in the application area of optical print inspection. The system is able to process hundreds of megabytes of image data per second coming from several high-speed/high-resolution cameras. Due to performance requirements, some functionality has been implemented on dedicated hardware based on a field programmable gate array (FPGA), which is coupled to a high-end digital signal processor (DSP). The paper discusses design considerations like partitioning of image processing algorithms between hardware and software. The main chapters focus on functionality implemented on the FPGA, including low-level image processing algorithms (flat-field correction, image pyramid generation, neighborhood operations) and advanced processing units (programmable arithmetic unit, geometry unit). Verification issues for the complex system are also addressed. The paper concludes with a summary of the FPGA resource usage and some performance results. [ABSTRACT FROM AUTHOR]
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Database:	Engineering Source

Description
Abstract:	This paper describes the design of a scalable high-performance vision system which is used in the application area of optical print inspection. The system is able to process hundreds of megabytes of image data per second coming from several high-speed/high-resolution cameras. Due to performance requirements, some functionality has been implemented on dedicated hardware based on a field programmable gate array (FPGA), which is coupled to a high-end digital signal processor (DSP). The paper discusses design considerations like partitioning of image processing algorithms between hardware and software. The main chapters focus on functionality implemented on the FPGA, including low-level image processing algorithms (flat-field correction, image pyramid generation, neighborhood operations) and advanced processing units (programmable arithmetic unit, geometry unit). Verification issues for the complex system are also addressed. The paper concludes with a summary of the FPGA resource usage and some performance results. [ABSTRACT FROM AUTHOR]
ISSN:	16873955
DOI:	10.1155/2007/71794