Bibliographic Details
| Title: |
Reducing clock jitter by using Muller-C elements. |
| Authors: |
Winstead, C.1 winstead@engineering.usu.edu, Hamoui, M. El1 |
| Source: |
Electronics Letters (Institution of Engineering & Technology). 1/29/2009, Vol. 45 Issue 3, p150-151. 2p. 1 Diagram, 2 Graphs. |
| Subjects: |
Electronics, Very large scale circuit integration, Digital-to-analog converters, Digital electronics, Digital incremental plotters |
| Abstract: |
A simple method for reducing the cycle-to-cycle jitter of clock signals is described. The method uses Muller-C elements to merge redundant clock signals. If the two clock signals have nearly the same average phase and independently-distributed phase noise, then the jitter at the Muller-C element's output is less than that of the input signals. This method can be used to reduce jitter in sampling clocks for analogue-to-digital conversion, and in clock distribution networks for VLSI systems. [ABSTRACT FROM AUTHOR] |
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| Database: |
Engineering Source |
