Multi-valued logic mapping of resistive short and open delay-fault testing in deep sub-micron technologies
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| Title: | Multi-valued logic mapping of resistive short and open delay-fault testing in deep sub-micron technologies |
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| Authors: | Javaheri, Reza1, Sedaghat, Reza http://www.ee.ryerson.ca/opr |
| Source: | Microelectronics Reliability. Feb2009, Vol. 49 Issue 2, p178-185. 8p. |
| Subjects: | Semiconductor defects, Delay faults (Semiconductors), Semiconductors testing, Many-valued logic, Algorithms, Mathematical mappings, Technological innovations |
| Abstract: | Abstract: In advanced technologies an increasing proportion of defects manifest themselves as small delay faults. Most of today’s advanced delay-fault algorithms are able to propagate those delay faults which create logic or glitch faults. An algorithm is proposed for circuit fault diagnosis in deep sub-micron technology to propagate the actual timing faults as well as those delay faults that eventually create logic faults to the primary outputs. Unlike the backtrack algorithm that predicts the fault site by tracing the syndrome at a faulty output back into the circuit, this approach propagates the fault from the fault site by mapping a nine-valued voltage model on top of a five-valued voltage model. In such a forward approach, accuracy is greatly increased since all composite syndromes at all faulty outputs are considered simultaneously. As a result, the proposed approach is applicable even when the delay size is relatively small. Experimental results show that the number of fault candidates produced by this approach is considerable. [Copyright &y& Elsevier] |
| Copyright of Microelectronics Reliability is the property of Pergamon Press - An Imprint of Elsevier Science and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 36393476 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Multi-valued logic mapping of resistive short and open delay-fault testing in deep sub-micron technologies – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Javaheri%2C+Reza%22">Javaheri, Reza</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Sedaghat%2C+Reza%22">Sedaghat, Reza</searchLink><i> http://www.ee.ryerson.ca/opr</i> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Microelectronics+Reliability%22">Microelectronics Reliability</searchLink>. Feb2009, Vol. 49 Issue 2, p178-185. 8p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Semiconductor+defects%22">Semiconductor defects</searchLink><br /><searchLink fieldCode="DE" term="%22Delay+faults+%28Semiconductors%29%22">Delay faults (Semiconductors)</searchLink><br /><searchLink fieldCode="DE" term="%22Semiconductors+testing%22">Semiconductors testing</searchLink><br /><searchLink fieldCode="DE" term="%22Many-valued+logic%22">Many-valued logic</searchLink><br /><searchLink fieldCode="DE" term="%22Algorithms%22">Algorithms</searchLink><br /><searchLink fieldCode="DE" term="%22Mathematical+mappings%22">Mathematical mappings</searchLink><br /><searchLink fieldCode="DE" term="%22Technological+innovations%22">Technological innovations</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: Abstract: In advanced technologies an increasing proportion of defects manifest themselves as small delay faults. Most of today’s advanced delay-fault algorithms are able to propagate those delay faults which create logic or glitch faults. An algorithm is proposed for circuit fault diagnosis in deep sub-micron technology to propagate the actual timing faults as well as those delay faults that eventually create logic faults to the primary outputs. Unlike the backtrack algorithm that predicts the fault site by tracing the syndrome at a faulty output back into the circuit, this approach propagates the fault from the fault site by mapping a nine-valued voltage model on top of a five-valued voltage model. In such a forward approach, accuracy is greatly increased since all composite syndromes at all faulty outputs are considered simultaneously. As a result, the proposed approach is applicable even when the delay size is relatively small. Experimental results show that the number of fault candidates produced by this approach is considerable. [Copyright &y& Elsevier] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of Microelectronics Reliability is the property of Pergamon Press - An Imprint of Elsevier Science and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1016/j.microrel.2008.11.010 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 8 StartPage: 178 Subjects: – SubjectFull: Semiconductor defects Type: general – SubjectFull: Delay faults (Semiconductors) Type: general – SubjectFull: Semiconductors testing Type: general – SubjectFull: Many-valued logic Type: general – SubjectFull: Algorithms Type: general – SubjectFull: Mathematical mappings Type: general – SubjectFull: Technological innovations Type: general Titles: – TitleFull: Multi-valued logic mapping of resistive short and open delay-fault testing in deep sub-micron technologies Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Javaheri, Reza – PersonEntity: Name: NameFull: Sedaghat, Reza IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 02 Text: Feb2009 Type: published Y: 2009 Identifiers: – Type: issn-print Value: 00262714 Numbering: – Type: volume Value: 49 – Type: issue Value: 2 Titles: – TitleFull: Microelectronics Reliability Type: main |
| ResultId | 1 |
