Synthesis of space optimal systolic arrays for band matrix-vector multiplication.

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Bibliographic Details
Title: Synthesis of space optimal systolic arrays for band matrix-vector multiplication.
Authors: Milovanović, E.1 ema@elfak.ni.ac.yu, Bekakos, M.2, Milovanović, I.1
Source: Journal of Supercomputing. Sep2009, Vol. 49 Issue 3, p269-290. 22p. 10 Diagrams, 2 Charts, 2 Graphs.
Subjects: Systolic array circuits, Matrices (Mathematics), Mathematical transformations, Graphic methods, Integrated circuits
Abstract: In this paper, we consider the implementation of a product c= A b, where A is N1× N3 band matrix with bandwidth ω and b is a vector of size N3×1, on bidirectional and unidirectional linear systolic arrays (BLSA and ULSA, respectively). We distinguish the cases when the matrix bandwidth ω is 1≤ ω≤ N3 and N3≤ ω≤ N1+ N3−1. A modification of the systolic array synthesis procedure based on data dependencies and space-time transformations of data dependency graph is proposed. The modification enables obtaining both BLSA and ULSA with an optimal number of processing elements (PEs) regardless of the matrix bandwidth. The execution time of the synthesized arrays has been minimized. We derive explicit formulas for the synthesis of these arrays. The performances of the designed arrays are discussed and compared to the performances of the arrays obtained by the standard design procedure. [ABSTRACT FROM AUTHOR]
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Database: Engineering Source
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Abstract:In this paper, we consider the implementation of a product c= A b, where A is N1× N3 band matrix with bandwidth ω and b is a vector of size N3×1, on bidirectional and unidirectional linear systolic arrays (BLSA and ULSA, respectively). We distinguish the cases when the matrix bandwidth ω is 1≤ ω≤ N3 and N3≤ ω≤ N1+ N3−1. A modification of the systolic array synthesis procedure based on data dependencies and space-time transformations of data dependency graph is proposed. The modification enables obtaining both BLSA and ULSA with an optimal number of processing elements (PEs) regardless of the matrix bandwidth. The execution time of the synthesized arrays has been minimized. We derive explicit formulas for the synthesis of these arrays. The performances of the designed arrays are discussed and compared to the performances of the arrays obtained by the standard design procedure. [ABSTRACT FROM AUTHOR]
ISSN:09208542
DOI:10.1007/s11227-008-0241-x