Bibliographic Details
| Title: |
One-Pass Compilation of Arithmetic Expressions for a Parallel Processor. |
| Authors: |
Stone, Harold S.1 |
| Source: |
Communications of the ACM. Apr1967, Vol. 10 Issue 4, p220-223. 4p. 1 Diagram. |
| Subjects: |
Parallel processing, Computer arithmetic & logic units, Compilers (Computer programs), Arithmetic, Algorithms, Computer circuits |
| Abstract: |
Under the assumption that a processor may have a multiplicity of arithmetic units, a compiler for such a processor should produce object code to take advantage of possible parallelism of operation. Most of the presently known compilation techniques are inadequate for such a processor because they produce expression structures that must be evaluated serially. A technique is presented here for compiling arithmetic expressions into structures that can be evaluated with a high degree of parallelism. The algorithm is a variant of the so-called "top-down" analysis technique, and requires only one pass of the input text. [ABSTRACT FROM AUTHOR] |
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| Database: |
Engineering Source |
