Design and Manufacturing of Micro Via-In-Pad Substrates for Solder Bumped Flip Chip Applications.

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Title: Design and Manufacturing of Micro Via-In-Pad Substrates for Solder Bumped Flip Chip Applications.
Authors: Lau, John, Chang, Chris, Lee, Ricky, Chen, Tsung-Yuan, Cheng, David, Tseng, Tzyy Jang, Lin, Dyna
Source: Journal of Electronics Manufacturing. Mar2000, Vol. 10 Issue 1, p79. 9p.
Subjects: Integrated circuits, Chip scale packaging
Abstract: A novel and low-cost micro via-in-pad (VIP) substrate for supporting a solder bumped flip chip is presented in this study. Emphasis is placed on the design, materials, process, manufacturing, and reliability of the micro VIP substrate of a chip scale package (CSP), and of the micro VIP CSP printed circuit board (PCB) assembly. Cross-sections of samples are examined for a better understanding of the solder bump, CSP redistribution, VIP, and solder joint. Non-linear finite element analyses are used to determine the stress and strain in the copper VIP and the solder joint. Time-dependent non-linear analysis is used to predict the thermal-fatigue life of the VIP solder joint. [ABSTRACT FROM AUTHOR]
Copyright of Journal of Electronics Manufacturing is the property of World Scientific Publishing Company and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
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DbLabel: Engineering Source
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PubType: Academic Journal
PubTypeId: academicJournal
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  Data: Design and Manufacturing of Micro Via-In-Pad Substrates for Solder Bumped Flip Chip Applications.
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  Data: <searchLink fieldCode="AR" term="%22Lau%2C+John%22">Lau, John</searchLink><br /><searchLink fieldCode="AR" term="%22Chang%2C+Chris%22">Chang, Chris</searchLink><br /><searchLink fieldCode="AR" term="%22Lee%2C+Ricky%22">Lee, Ricky</searchLink><br /><searchLink fieldCode="AR" term="%22Chen%2C+Tsung-Yuan%22">Chen, Tsung-Yuan</searchLink><br /><searchLink fieldCode="AR" term="%22Cheng%2C+David%22">Cheng, David</searchLink><br /><searchLink fieldCode="AR" term="%22Tseng%2C+Tzyy+Jang%22">Tseng, Tzyy Jang</searchLink><br /><searchLink fieldCode="AR" term="%22Lin%2C+Dyna%22">Lin, Dyna</searchLink>
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  Data: <searchLink fieldCode="JN" term="%22Journal+of+Electronics+Manufacturing%22">Journal of Electronics Manufacturing</searchLink>. Mar2000, Vol. 10 Issue 1, p79. 9p.
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  Data: <searchLink fieldCode="DE" term="%22Integrated+circuits%22">Integrated circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Chip+scale+packaging%22">Chip scale packaging</searchLink>
– Name: Abstract
  Label: Abstract
  Group: Ab
  Data: A novel and low-cost micro via-in-pad (VIP) substrate for supporting a solder bumped flip chip is presented in this study. Emphasis is placed on the design, materials, process, manufacturing, and reliability of the micro VIP substrate of a chip scale package (CSP), and of the micro VIP CSP printed circuit board (PCB) assembly. Cross-sections of samples are examined for a better understanding of the solder bump, CSP redistribution, VIP, and solder joint. Non-linear finite element analyses are used to determine the stress and strain in the copper VIP and the solder joint. Time-dependent non-linear analysis is used to predict the thermal-fatigue life of the VIP solder joint. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of Journal of Electronics Manufacturing is the property of World Scientific Publishing Company and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Value: 10.1142/S0960313100000101
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        Text: English
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        PageCount: 9
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              Text: Mar2000
              Type: published
              Y: 2000
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