Vedic Mathematics Based 32-Bit Multiplier Design for High Speed Low Power Processors.

Saved in:

Bibliographic Details
Title:	Vedic Mathematics Based 32-Bit Multiplier Design for High Speed Low Power Processors.
Authors:	Saha, P.¹, Banerjee, A.², Dandapat, A.³, Bhattacharyya, P.¹ pbetcbesu@yahoo.com
Source:	International Journal on Smart Sensing & Intelligent Systems. Jun2011, Vol. 4 Issue 2, p268-284. 17p. 8 Diagrams, 2 Graphs.
Subjects:	Mathematics methodology, Arithmetic, Sūtras (Buddhism), Boolean algebra, Parallel processing
Abstract:	Vedic Mathematics is the ancient methodology of Indian mathematics which has a unique technique for arithmetic computations based on 16 Sutras (Formulae). Transistor level implementation (ASIC) of Vedic Mathematics based 32-bit multiplier for high speed low power processor is reported in this paper. Simple Boolean logic is combined with 'Vedic' formulas, which reduces the partial products and sums generated in one step, reduces the carry propagation from LSB to MSB. The implementation methodology ensure substantial reduction of propagation delay in comparison with Wallace Tree (WTM), modified Booth Algorithm (MBA), Baugh Wooley (BWM) and Row Bypassing and Parallel Architecture (RBPA) based implementation which are most commonly used architectures. The functionality of these circuits was checked and performance parameters like propagation delay and dynamic power consumption were calculated by spice spectre using standard 90nm CMOS technology. The propagation delay of the resulting 32×32 multiplier was only ∼1.06 us and consumes ∼132 uW power. The implementation offered significant improvement in terms of delay and power from earlier reported ones. [ABSTRACT FROM AUTHOR]
	Copyright of International Journal on Smart Sensing & Intelligent Systems is the property of Paradigm Publishing Services and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database:	Engineering Source

Description
Abstract:	Vedic Mathematics is the ancient methodology of Indian mathematics which has a unique technique for arithmetic computations based on 16 Sutras (Formulae). Transistor level implementation (ASIC) of Vedic Mathematics based 32-bit multiplier for high speed low power processor is reported in this paper. Simple Boolean logic is combined with 'Vedic' formulas, which reduces the partial products and sums generated in one step, reduces the carry propagation from LSB to MSB. The implementation methodology ensure substantial reduction of propagation delay in comparison with Wallace Tree (WTM), modified Booth Algorithm (MBA), Baugh Wooley (BWM) and Row Bypassing and Parallel Architecture (RBPA) based implementation which are most commonly used architectures. The functionality of these circuits was checked and performance parameters like propagation delay and dynamic power consumption were calculated by spice spectre using standard 90nm CMOS technology. The propagation delay of the resulting 32×32 multiplier was only ∼1.06 us and consumes ∼132 uW power. The implementation offered significant improvement in terms of delay and power from earlier reported ones. [ABSTRACT FROM AUTHOR]
ISSN:	11785608
DOI:	10.21307/ijssis-2017-439