Multi-core and many-core shared-memory parallel raycasting volume rendering optimization and tuning.
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| Title: | Multi-core and many-core shared-memory parallel raycasting volume rendering optimization and tuning. |
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| Authors: | Bethel, E Wes1, Howison, Mark2 |
| Source: | International Journal of High Performance Computing Applications. Nov2012, Vol. 26 Issue 4, p399-412. 14p. |
| Subjects: | Graphics processing units, Central processing units, Parallel computers, Memory, Algorithms, Performance evaluation |
| Abstract: | Given the computing industry trend of increasing processing capacity by adding more cores to a chip, the focus of this work is tuning the performance of a staple visualization algorithm, raycasting volume rendering, for shared-memory parallelism on multi-core CPUs and many-core GPUs. Our approach is to vary tunable algorithmic settings, along with known algorithmic optimizations and two different memory layouts, and measure performance in terms of absolute runtime and L2 memory cache misses. Our results indicate there is a wide variation in runtime performance on all platforms, as much as 254% for the tunable parameters we test on multi-core CPUs and 265% on many-core GPUs, and the optimal configurations vary across platforms, often in a non-obvious way. For example, our results indicate the optimal configurations on the GPU occur at a crossover point between those that maintain good cache utilization and those that saturate computational throughput. This result is likely to be extremely difficult to predict with an empirical performance model for this particular algorithm because it has an unstructured memory access pattern that varies locally for individual rays and globally for the selected viewpoint. Our results also show that optimal parameters on modern architectures are markedly different from those in previous studies run on older architectures. In addition, given the dramatic performance variation across platforms for both optimal algorithm settings and performance results, there is a clear benefit for production visualization and analysis codes to adopt a strategy for performance optimization through auto-tuning. These benefits will likely become more pronounced in the future as the number of cores per chip and the cost of moving data through the memory hierarchy both increase. [ABSTRACT FROM AUTHOR] |
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| Database: | Engineering Source |
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