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Improving Throughput of Power-Constrained Many-Core Processors Based on Unreliable Devices.

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Bibliographic Details
Title: Improving Throughput of Power-Constrained Many-Core Processors Based on Unreliable Devices.
Authors: Wang, Hao1, Kim, Nam Sung1
Source: IEEE Micro. Jul2013, Vol. 33 Issue 4, p16-24. 9p.
Subjects: Microprocessor energy consumption, Complementary metal oxide semiconductors, Carbon nanotubes, CMOS integrated circuits, Integrated circuit energy consumption
Abstract: It has been reported that carbon nanotube (CNT) devices are faster and consume less power than CMOS devices. However, current CNT devices exhibit a higher defect rate than CMOS devices. To reduce the defect rate of CNT devices, a device-level redundancy technique can be adopted. However, more device-level redundancy in turn increases area, delay, and power consumption of integrated circuits (ICs). In this article, the authors propose to use slightly less device-level redundancy than required for all processor cores to be defect-free for a yield target, which makes cores smaller, faster, and more power efficient. Although some cores can be defective with less device-level redundancy, many-core processors can tolerate some defective cores by design. Under the same power and yield constraints, the authors demonstrate that a CNT processor with less device-level redundancy can provide 1.75 times higher throughput despite also being nearly 2 times smaller than a CNT processor that has more device-level redundancy and that also makes all cores defect free. [ABSTRACT FROM PUBLISHER]
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Database: Engineering Source
Description
Abstract:It has been reported that carbon nanotube (CNT) devices are faster and consume less power than CMOS devices. However, current CNT devices exhibit a higher defect rate than CMOS devices. To reduce the defect rate of CNT devices, a device-level redundancy technique can be adopted. However, more device-level redundancy in turn increases area, delay, and power consumption of integrated circuits (ICs). In this article, the authors propose to use slightly less device-level redundancy than required for all processor cores to be defect-free for a yield target, which makes cores smaller, faster, and more power efficient. Although some cores can be defective with less device-level redundancy, many-core processors can tolerate some defective cores by design. Under the same power and yield constraints, the authors demonstrate that a CNT processor with less device-level redundancy can provide 1.75 times higher throughput despite also being nearly 2 times smaller than a CNT processor that has more device-level redundancy and that also makes all cores defect free. [ABSTRACT FROM PUBLISHER]
ISSN:02721732
DOI:10.1109/MM.2013.69