View in EDS

Improving Throughput of Power-Constrained Many-Core Processors Based on Unreliable Devices.

Saved in:
Bibliographic Details
Title: Improving Throughput of Power-Constrained Many-Core Processors Based on Unreliable Devices.
Authors: Wang, Hao1, Kim, Nam Sung1
Source: IEEE Micro. Jul2013, Vol. 33 Issue 4, p16-24. 9p.
Subjects: Microprocessor energy consumption, Complementary metal oxide semiconductors, Carbon nanotubes, CMOS integrated circuits, Integrated circuit energy consumption
Abstract: It has been reported that carbon nanotube (CNT) devices are faster and consume less power than CMOS devices. However, current CNT devices exhibit a higher defect rate than CMOS devices. To reduce the defect rate of CNT devices, a device-level redundancy technique can be adopted. However, more device-level redundancy in turn increases area, delay, and power consumption of integrated circuits (ICs). In this article, the authors propose to use slightly less device-level redundancy than required for all processor cores to be defect-free for a yield target, which makes cores smaller, faster, and more power efficient. Although some cores can be defective with less device-level redundancy, many-core processors can tolerate some defective cores by design. Under the same power and yield constraints, the authors demonstrate that a CNT processor with less device-level redundancy can provide 1.75 times higher throughput despite also being nearly 2 times smaller than a CNT processor that has more device-level redundancy and that also makes all cores defect free. [ABSTRACT FROM PUBLISHER]
Copyright of IEEE Micro is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
FullText Text:
  Availability: 0
Header DbId: egs
DbLabel: Engineering Source
An: 89975687
AccessLevel: 6
PubType: Academic Journal
PubTypeId: academicJournal
PreciseRelevancyScore: 0
IllustrationInfo
Items – Name: Title
  Label: Title
  Group: Ti
  Data: Improving Throughput of Power-Constrained Many-Core Processors Based on Unreliable Devices.
– Name: Author
  Label: Authors
  Group: Au
  Data: <searchLink fieldCode="AR" term="%22Wang%2C+Hao%22">Wang, Hao</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Kim%2C+Nam+Sung%22">Kim, Nam Sung</searchLink><relatesTo>1</relatesTo>
– Name: TitleSource
  Label: Source
  Group: Src
  Data: <searchLink fieldCode="JN" term="%22IEEE+Micro%22">IEEE Micro</searchLink>. Jul2013, Vol. 33 Issue 4, p16-24. 9p.
– Name: Subject
  Label: Subjects
  Group: Su
  Data: <searchLink fieldCode="DE" term="%22Microprocessor+energy+consumption%22">Microprocessor energy consumption</searchLink><br /><searchLink fieldCode="DE" term="%22Complementary+metal+oxide+semiconductors%22">Complementary metal oxide semiconductors</searchLink><br /><searchLink fieldCode="DE" term="%22Carbon+nanotubes%22">Carbon nanotubes</searchLink><br /><searchLink fieldCode="DE" term="%22CMOS+integrated+circuits%22">CMOS integrated circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Integrated+circuit+energy+consumption%22">Integrated circuit energy consumption</searchLink>
– Name: Abstract
  Label: Abstract
  Group: Ab
  Data: It has been reported that carbon nanotube (CNT) devices are faster and consume less power than CMOS devices. However, current CNT devices exhibit a higher defect rate than CMOS devices. To reduce the defect rate of CNT devices, a device-level redundancy technique can be adopted. However, more device-level redundancy in turn increases area, delay, and power consumption of integrated circuits (ICs). In this article, the authors propose to use slightly less device-level redundancy than required for all processor cores to be defect-free for a yield target, which makes cores smaller, faster, and more power efficient. Although some cores can be defective with less device-level redundancy, many-core processors can tolerate some defective cores by design. Under the same power and yield constraints, the authors demonstrate that a CNT processor with less device-level redundancy can provide 1.75 times higher throughput despite also being nearly 2 times smaller than a CNT processor that has more device-level redundancy and that also makes all cores defect free. [ABSTRACT FROM PUBLISHER]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of IEEE Micro is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
PLink https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=egs&AN=89975687
RecordInfo BibRecord:
  BibEntity:
    Identifiers:
      – Type: doi
        Value: 10.1109/MM.2013.69
    Languages:
      – Code: eng
        Text: English
    PhysicalDescription:
      Pagination:
        PageCount: 9
        StartPage: 16
    Subjects:
      – SubjectFull: Microprocessor energy consumption
        Type: general
      – SubjectFull: Complementary metal oxide semiconductors
        Type: general
      – SubjectFull: Carbon nanotubes
        Type: general
      – SubjectFull: CMOS integrated circuits
        Type: general
      – SubjectFull: Integrated circuit energy consumption
        Type: general
    Titles:
      – TitleFull: Improving Throughput of Power-Constrained Many-Core Processors Based on Unreliable Devices.
        Type: main
  BibRelationships:
    HasContributorRelationships:
      – PersonEntity:
          Name:
            NameFull: Wang, Hao
      – PersonEntity:
          Name:
            NameFull: Kim, Nam Sung
    IsPartOfRelationships:
      – BibEntity:
          Dates:
            – D: 01
              M: 07
              Text: Jul2013
              Type: published
              Y: 2013
          Identifiers:
            – Type: issn-print
              Value: 02721732
          Numbering:
            – Type: volume
              Value: 33
            – Type: issue
              Value: 4
          Titles:
            – TitleFull: IEEE Micro
              Type: main
ResultId 1