AN INTEGRATED SIMULATION INFRASTRUCTURE FOR THE ENTIRE MEMORY HIERARCHY: CACHE , DRAM, NONVOLATI LE MEMORY, AND DISK.

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Bibliographic Details
Title:	AN INTEGRATED SIMULATION INFRASTRUCTURE FOR THE ENTIRE MEMORY HIERARCHY: CACHE , DRAM, NONVOLATI LE MEMORY, AND DISK.
Authors:	Stevens, Jim¹, Tschirhart, Paul¹, Mu-Tien Chang¹, Bhati, Ishwar¹, Enns, Peter¹, Greensky, James², Chisti, Zeshan², Shih-Lien Lu², Jacob, Bruce¹
Source:	Intel Technology Journal. 2013, Vol. 17 Issue 1, p184-200. 17p. 3 Diagrams, 1 Chart, 7 Graphs.
Subjects:	Computer simulation, Memory hierarchy (Computer science), Cache memory, Dynamic random access memory, Big data, Multicore processors
Abstract:	As computer systems evolve towards exascale and attempt to meet new application requirements such as big data, conventional memory technologies and architectures are no longer adequate in terms of bandwidth, power, capacity, or resilience. In order to understand these problems and analyze potential solutions, an accurate simulation environment that captures all of the complex interactions of the modern computer system is essential. In this article, we present an integrated simulation infrastructure for the entire memory hierarchy, including the processor cache, the DRAM main memory system, and nonvolatile memory, whether it is integrated as hybrid main memory or as a solid state drive. The memory simulations we present are integrated into a full system simulation, which enables studying the memory hierarchy with a faithful representation of a modern x86 multicore processor. The simulated hardware is capable of running unmodified operating systems and user software, which generates authentic memory access patterns for memory hierarchy studies. To demonstrate the capabilities of our infrastructure we include a series of experimental examples that utilize the cache, DRAM main memory, and nonvolatile memory modules [ABSTRACT FROM AUTHOR]
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Database:	Engineering Source

Description
Abstract:	As computer systems evolve towards exascale and attempt to meet new application requirements such as big data, conventional memory technologies and architectures are no longer adequate in terms of bandwidth, power, capacity, or resilience. In order to understand these problems and analyze potential solutions, an accurate simulation environment that captures all of the complex interactions of the modern computer system is essential. In this article, we present an integrated simulation infrastructure for the entire memory hierarchy, including the processor cache, the DRAM main memory system, and nonvolatile memory, whether it is integrated as hybrid main memory or as a solid state drive. The memory simulations we present are integrated into a full system simulation, which enables studying the memory hierarchy with a faithful representation of a modern x86 multicore processor. The simulated hardware is capable of running unmodified operating systems and user software, which generates authentic memory access patterns for memory hierarchy studies. To demonstrate the capabilities of our infrastructure we include a series of experimental examples that utilize the cache, DRAM main memory, and nonvolatile memory modules [ABSTRACT FROM AUTHOR]
ISSN:	1535864X