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AN INTEGRATED SIMULATION INFRASTRUCTURE FOR THE ENTIRE MEMORY HIERARCHY: CACHE , DRAM, NONVOLATI LE MEMORY, AND DISK.

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Title: AN INTEGRATED SIMULATION INFRASTRUCTURE FOR THE ENTIRE MEMORY HIERARCHY: CACHE , DRAM, NONVOLATI LE MEMORY, AND DISK.
Authors: Stevens, Jim1, Tschirhart, Paul1, Mu-Tien Chang1, Bhati, Ishwar1, Enns, Peter1, Greensky, James2, Chisti, Zeshan2, Shih-Lien Lu2, Jacob, Bruce1
Source: Intel Technology Journal. 2013, Vol. 17 Issue 1, p184-200. 17p. 3 Diagrams, 1 Chart, 7 Graphs.
Subjects: Computer simulation, Memory hierarchy (Computer science), Cache memory, Dynamic random access memory, Big data, Multicore processors
Abstract: As computer systems evolve towards exascale and attempt to meet new application requirements such as big data, conventional memory technologies and architectures are no longer adequate in terms of bandwidth, power, capacity, or resilience. In order to understand these problems and analyze potential solutions, an accurate simulation environment that captures all of the complex interactions of the modern computer system is essential. In this article, we present an integrated simulation infrastructure for the entire memory hierarchy, including the processor cache, the DRAM main memory system, and nonvolatile memory, whether it is integrated as hybrid main memory or as a solid state drive. The memory simulations we present are integrated into a full system simulation, which enables studying the memory hierarchy with a faithful representation of a modern x86 multicore processor. The simulated hardware is capable of running unmodified operating systems and user software, which generates authentic memory access patterns for memory hierarchy studies. To demonstrate the capabilities of our infrastructure we include a series of experimental examples that utilize the cache, DRAM main memory, and nonvolatile memory modules [ABSTRACT FROM AUTHOR]
Copyright of Intel Technology Journal is the property of Intel Corporation and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
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  Data: AN INTEGRATED SIMULATION INFRASTRUCTURE FOR THE ENTIRE MEMORY HIERARCHY: CACHE , DRAM, NONVOLATI LE MEMORY, AND DISK.
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  Data: <searchLink fieldCode="JN" term="%22Intel+Technology+Journal%22">Intel Technology Journal</searchLink>. 2013, Vol. 17 Issue 1, p184-200. 17p. 3 Diagrams, 1 Chart, 7 Graphs.
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  Data: <searchLink fieldCode="DE" term="%22Computer+simulation%22">Computer simulation</searchLink><br /><searchLink fieldCode="DE" term="%22Memory+hierarchy+%28Computer+science%29%22">Memory hierarchy (Computer science)</searchLink><br /><searchLink fieldCode="DE" term="%22Cache+memory%22">Cache memory</searchLink><br /><searchLink fieldCode="DE" term="%22Dynamic+random+access+memory%22">Dynamic random access memory</searchLink><br /><searchLink fieldCode="DE" term="%22Big+data%22">Big data</searchLink><br /><searchLink fieldCode="DE" term="%22Multicore+processors%22">Multicore processors</searchLink>
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  Data: As computer systems evolve towards exascale and attempt to meet new application requirements such as big data, conventional memory technologies and architectures are no longer adequate in terms of bandwidth, power, capacity, or resilience. In order to understand these problems and analyze potential solutions, an accurate simulation environment that captures all of the complex interactions of the modern computer system is essential. In this article, we present an integrated simulation infrastructure for the entire memory hierarchy, including the processor cache, the DRAM main memory system, and nonvolatile memory, whether it is integrated as hybrid main memory or as a solid state drive. The memory simulations we present are integrated into a full system simulation, which enables studying the memory hierarchy with a faithful representation of a modern x86 multicore processor. The simulated hardware is capable of running unmodified operating systems and user software, which generates authentic memory access patterns for memory hierarchy studies. To demonstrate the capabilities of our infrastructure we include a series of experimental examples that utilize the cache, DRAM main memory, and nonvolatile memory modules [ABSTRACT FROM AUTHOR]
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  Data: <i>Copyright of Intel Technology Journal is the property of Intel Corporation and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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