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Recomputing with Permuted Operands: A Concurrent Error Detection Approach.

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Title: Recomputing with Permuted Operands: A Concurrent Error Detection Approach.
Authors: Guo, Xiaofei1, Karri, Ramesh1
Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems. Oct2013, Vol. 32 Issue 10, p1595-1608. 14p.
Subjects: Concurrent error detection, Reliability in engineering, Field programmable gate arrays, Block ciphers, Integrated circuits, Data encryption, Computer architecture
Abstract: Naturally occurring and maliciously injected faults reduce the reliability of cryptographic hardware and may leak confidential information. We develop a concurrent error detection technique (CED) called recomputing with permuted operands (REPO). We show that it is cost effective in advanced encryption standard (AES) and a secure hash function Grøstl. We provide experimental results and formal proofs to show that REPO detects all single-bit and single-byte faults. Experimental results show that REPO achieves close to 100% fault coverage for multiple byte faults. The hardware and throughput overheads are compared with those of previously reported CED techniques on two Xilinx Virtex FPGAs. The hardware overhead is 12.4%–27.3%, and the throughput is 1.2–23 Gbps, depending on the AES architecture, FPGA family, and detection latency. The performance overhead ranges from 10% to 100% depending on the security level. Moreover, the proposed technique can be integrated into various block cipher modes of operation. We also discuss the limitation of REPO and its potential vulnerabilities. [ABSTRACT FROM PUBLISHER]
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Database: Engineering Source
Description
Abstract:Naturally occurring and maliciously injected faults reduce the reliability of cryptographic hardware and may leak confidential information. We develop a concurrent error detection technique (CED) called recomputing with permuted operands (REPO). We show that it is cost effective in advanced encryption standard (AES) and a secure hash function Grøstl. We provide experimental results and formal proofs to show that REPO detects all single-bit and single-byte faults. Experimental results show that REPO achieves close to 100% fault coverage for multiple byte faults. The hardware and throughput overheads are compared with those of previously reported CED techniques on two Xilinx Virtex FPGAs. The hardware overhead is 12.4%–27.3%, and the throughput is 1.2–23 Gbps, depending on the AES architecture, FPGA family, and detection latency. The performance overhead ranges from 10% to 100% depending on the security level. Moreover, the proposed technique can be integrated into various block cipher modes of operation. We also discuss the limitation of REPO and its potential vulnerabilities. [ABSTRACT FROM PUBLISHER]
ISSN:02780070
DOI:10.1109/TCAD.2013.2263037