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Recomputing with Permuted Operands: A Concurrent Error Detection Approach.

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Title: Recomputing with Permuted Operands: A Concurrent Error Detection Approach.
Authors: Guo, Xiaofei1, Karri, Ramesh1
Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems. Oct2013, Vol. 32 Issue 10, p1595-1608. 14p.
Subjects: Concurrent error detection, Reliability in engineering, Field programmable gate arrays, Block ciphers, Integrated circuits, Data encryption, Computer architecture
Abstract: Naturally occurring and maliciously injected faults reduce the reliability of cryptographic hardware and may leak confidential information. We develop a concurrent error detection technique (CED) called recomputing with permuted operands (REPO). We show that it is cost effective in advanced encryption standard (AES) and a secure hash function Grøstl. We provide experimental results and formal proofs to show that REPO detects all single-bit and single-byte faults. Experimental results show that REPO achieves close to 100% fault coverage for multiple byte faults. The hardware and throughput overheads are compared with those of previously reported CED techniques on two Xilinx Virtex FPGAs. The hardware overhead is 12.4%–27.3%, and the throughput is 1.2–23 Gbps, depending on the AES architecture, FPGA family, and detection latency. The performance overhead ranges from 10% to 100% depending on the security level. Moreover, the proposed technique can be integrated into various block cipher modes of operation. We also discuss the limitation of REPO and its potential vulnerabilities. [ABSTRACT FROM PUBLISHER]
Copyright of IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
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PubType: Academic Journal
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  Data: <searchLink fieldCode="DE" term="%22Concurrent+error+detection%22">Concurrent error detection</searchLink><br /><searchLink fieldCode="DE" term="%22Reliability+in+engineering%22">Reliability in engineering</searchLink><br /><searchLink fieldCode="DE" term="%22Field+programmable+gate+arrays%22">Field programmable gate arrays</searchLink><br /><searchLink fieldCode="DE" term="%22Block+ciphers%22">Block ciphers</searchLink><br /><searchLink fieldCode="DE" term="%22Integrated+circuits%22">Integrated circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Data+encryption%22">Data encryption</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+architecture%22">Computer architecture</searchLink>
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  Data: Naturally occurring and maliciously injected faults reduce the reliability of cryptographic hardware and may leak confidential information. We develop a concurrent error detection technique (CED) called recomputing with permuted operands (REPO). We show that it is cost effective in advanced encryption standard (AES) and a secure hash function Grøstl. We provide experimental results and formal proofs to show that REPO detects all single-bit and single-byte faults. Experimental results show that REPO achieves close to 100% fault coverage for multiple byte faults. The hardware and throughput overheads are compared with those of previously reported CED techniques on two Xilinx Virtex FPGAs. The hardware overhead is 12.4%–27.3%, and the throughput is 1.2–23 Gbps, depending on the AES architecture, FPGA family, and detection latency. The performance overhead ranges from 10% to 100% depending on the security level. Moreover, the proposed technique can be integrated into various block cipher modes of operation. We also discuss the limitation of REPO and its potential vulnerabilities. [ABSTRACT FROM PUBLISHER]
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  Label:
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  Data: <i>Copyright of IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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RecordInfo BibRecord:
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        Value: 10.1109/TCAD.2013.2263037
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      – Code: eng
        Text: English
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        PageCount: 14
        StartPage: 1595
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      – SubjectFull: Concurrent error detection
        Type: general
      – SubjectFull: Reliability in engineering
        Type: general
      – SubjectFull: Field programmable gate arrays
        Type: general
      – SubjectFull: Block ciphers
        Type: general
      – SubjectFull: Integrated circuits
        Type: general
      – SubjectFull: Data encryption
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      – SubjectFull: Computer architecture
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              M: 10
              Text: Oct2013
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              Y: 2013
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