Bibliographic Details
| Title: |
Access resistor modelling for EEPROM’s retention test vehicle. |
| Authors: |
Canet, P.1 pierre.canet@im2np.fr, Postel-Pellerin, J.1, Ogier, J.L.2 |
| Source: |
Microelectronics Reliability. Sep2013, Vol. 53 Issue 9-11, p1218-1223. 6p. |
| Subjects: |
Erasable programmable read-only memory, Electric resistors, Mathematical models, Threshold voltage, Computer programming, Gate array circuits |
| Abstract: |
Highlights: [•] Access resistor models explain maximum drain-source current in a CAST test vehicle. [•] The threshold voltage shift is explained by the sub-threshold slope. [•] Gate access resistor should have no effect on reading or programming. [•] Model is helpful to quantify the extrinsic cells in retention tests. [•] Memory lines inside array should not be longer than thousand cells per line. [Copyright &y& Elsevier] |
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Copyright of Microelectronics Reliability is the property of Pergamon Press - An Imprint of Elsevier Science and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) |
| Database: |
Engineering Source |
