View in EDS

Access resistor modelling for EEPROM’s retention test vehicle.

Saved in:
Bibliographic Details
Title: Access resistor modelling for EEPROM’s retention test vehicle.
Authors: Canet, P.1 pierre.canet@im2np.fr, Postel-Pellerin, J.1, Ogier, J.L.2
Source: Microelectronics Reliability. Sep2013, Vol. 53 Issue 9-11, p1218-1223. 6p.
Subjects: Erasable programmable read-only memory, Electric resistors, Mathematical models, Threshold voltage, Computer programming, Gate array circuits
Abstract: Highlights: [•] Access resistor models explain maximum drain-source current in a CAST test vehicle. [•] The threshold voltage shift is explained by the sub-threshold slope. [•] Gate access resistor should have no effect on reading or programming. [•] Model is helpful to quantify the extrinsic cells in retention tests. [•] Memory lines inside array should not be longer than thousand cells per line. [Copyright &y& Elsevier]
Copyright of Microelectronics Reliability is the property of Pergamon Press - An Imprint of Elsevier Science and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
FullText Text:
  Availability: 0
Header DbId: egs
DbLabel: Engineering Source
An: 91268361
AccessLevel: 6
PubType: Academic Journal
PubTypeId: academicJournal
PreciseRelevancyScore: 0
IllustrationInfo
Items – Name: Title
  Label: Title
  Group: Ti
  Data: Access resistor modelling for EEPROM’s retention test vehicle.
– Name: Author
  Label: Authors
  Group: Au
  Data: <searchLink fieldCode="AR" term="%22Canet%2C+P%2E%22">Canet, P.</searchLink><relatesTo>1</relatesTo><i> pierre.canet@im2np.fr</i><br /><searchLink fieldCode="AR" term="%22Postel-Pellerin%2C+J%2E%22">Postel-Pellerin, J.</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Ogier%2C+J%2EL%2E%22">Ogier, J.L.</searchLink><relatesTo>2</relatesTo>
– Name: TitleSource
  Label: Source
  Group: Src
  Data: <searchLink fieldCode="JN" term="%22Microelectronics+Reliability%22">Microelectronics Reliability</searchLink>. Sep2013, Vol. 53 Issue 9-11, p1218-1223. 6p.
– Name: Subject
  Label: Subjects
  Group: Su
  Data: <searchLink fieldCode="DE" term="%22Erasable+programmable+read-only+memory%22">Erasable programmable read-only memory</searchLink><br /><searchLink fieldCode="DE" term="%22Electric+resistors%22">Electric resistors</searchLink><br /><searchLink fieldCode="DE" term="%22Mathematical+models%22">Mathematical models</searchLink><br /><searchLink fieldCode="DE" term="%22Threshold+voltage%22">Threshold voltage</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+programming%22">Computer programming</searchLink><br /><searchLink fieldCode="DE" term="%22Gate+array+circuits%22">Gate array circuits</searchLink>
– Name: Abstract
  Label: Abstract
  Group: Ab
  Data: Highlights: [•] Access resistor models explain maximum drain-source current in a CAST test vehicle. [•] The threshold voltage shift is explained by the sub-threshold slope. [•] Gate access resistor should have no effect on reading or programming. [•] Model is helpful to quantify the extrinsic cells in retention tests. [•] Memory lines inside array should not be longer than thousand cells per line. [Copyright &y& Elsevier]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of Microelectronics Reliability is the property of Pergamon Press - An Imprint of Elsevier Science and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
PLink https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=egs&AN=91268361
RecordInfo BibRecord:
  BibEntity:
    Identifiers:
      – Type: doi
        Value: 10.1016/j.microrel.2013.07.008
    Languages:
      – Code: eng
        Text: English
    PhysicalDescription:
      Pagination:
        PageCount: 6
        StartPage: 1218
    Subjects:
      – SubjectFull: Erasable programmable read-only memory
        Type: general
      – SubjectFull: Electric resistors
        Type: general
      – SubjectFull: Mathematical models
        Type: general
      – SubjectFull: Threshold voltage
        Type: general
      – SubjectFull: Computer programming
        Type: general
      – SubjectFull: Gate array circuits
        Type: general
    Titles:
      – TitleFull: Access resistor modelling for EEPROM’s retention test vehicle.
        Type: main
  BibRelationships:
    HasContributorRelationships:
      – PersonEntity:
          Name:
            NameFull: Canet, P.
      – PersonEntity:
          Name:
            NameFull: Postel-Pellerin, J.
      – PersonEntity:
          Name:
            NameFull: Ogier, J.L.
    IsPartOfRelationships:
      – BibEntity:
          Dates:
            – D: 01
              M: 09
              Text: Sep2013
              Type: published
              Y: 2013
          Identifiers:
            – Type: issn-print
              Value: 00262714
          Numbering:
            – Type: volume
              Value: 53
            – Type: issue
              Value: 9-11
          Titles:
            – TitleFull: Microelectronics Reliability
              Type: main
ResultId 1