Design of Zero Skew Clock Tree for CMOS Image Sensor.

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Bibliographic Details
Title:	Design of Zero Skew Clock Tree for CMOS Image Sensor.
Authors:	Kansal, Shubhi¹ kansalshubhi@yahoo.com
Source:	IUP Journal of Electrical & Electronics Engineering. Oct2013, Vol. 6 Issue 4, p7-12. 6p.
Subjects:	Complementary metal oxide semiconductors, Clock distribution networks, Skewness (Probability theory), Electronic systems, Electronic industries
Abstract:	Clock tree synthesis is the heart of the design and clock tree network robustness is one of the important quality metrics of the SoC design. With the technology advancement over past one-and-a-half decades, clock tree robustness has become an even more critical factor affecting SoC performance. There are some quality parameters which need to be kept in mind regarding clock tree design like minimum latency, minimum skew and duty cycle (Agarwal and Garg, 2012). A clock tree must be designed with these considerations and symmetrical cells having similar rise-fall delays should be used to build the clock tree. Keeping all the above parameters in mind, a clock tree has been designed for stitched CMOS image sensor. [ABSTRACT FROM AUTHOR]
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Database:	Engineering Source

Description
Abstract:	Clock tree synthesis is the heart of the design and clock tree network robustness is one of the important quality metrics of the SoC design. With the technology advancement over past one-and-a-half decades, clock tree robustness has become an even more critical factor affecting SoC performance. There are some quality parameters which need to be kept in mind regarding clock tree design like minimum latency, minimum skew and duty cycle (Agarwal and Garg, 2012). A clock tree must be designed with these considerations and symmetrical cells having similar rise-fall delays should be used to build the clock tree. Keeping all the above parameters in mind, a clock tree has been designed for stitched CMOS image sensor. [ABSTRACT FROM AUTHOR]
ISSN:	2583519X