Design of Zero Skew Clock Tree for CMOS Image Sensor.
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| Title: | Design of Zero Skew Clock Tree for CMOS Image Sensor. |
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| Authors: | Kansal, Shubhi1 kansalshubhi@yahoo.com |
| Source: | IUP Journal of Electrical & Electronics Engineering. Oct2013, Vol. 6 Issue 4, p7-12. 6p. |
| Subjects: | Complementary metal oxide semiconductors, Clock distribution networks, Skewness (Probability theory), Electronic systems, Electronic industries |
| Abstract: | Clock tree synthesis is the heart of the design and clock tree network robustness is one of the important quality metrics of the SoC design. With the technology advancement over past one-and-a-half decades, clock tree robustness has become an even more critical factor affecting SoC performance. There are some quality parameters which need to be kept in mind regarding clock tree design like minimum latency, minimum skew and duty cycle (Agarwal and Garg, 2012). A clock tree must be designed with these considerations and symmetrical cells having similar rise-fall delays should be used to build the clock tree. Keeping all the above parameters in mind, a clock tree has been designed for stitched CMOS image sensor. [ABSTRACT FROM AUTHOR] |
| Copyright of IUP Journal of Electrical & Electronics Engineering is the property of IUP Publications and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
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| Header | DbId: egs DbLabel: Engineering Source An: 92607003 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Design of Zero Skew Clock Tree for CMOS Image Sensor. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Kansal%2C+Shubhi%22">Kansal, Shubhi</searchLink><relatesTo>1</relatesTo><i> kansalshubhi@yahoo.com</i> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22IUP+Journal+of+Electrical+%26+Electronics+Engineering%22">IUP Journal of Electrical & Electronics Engineering</searchLink>. Oct2013, Vol. 6 Issue 4, p7-12. 6p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Complementary+metal+oxide+semiconductors%22">Complementary metal oxide semiconductors</searchLink><br /><searchLink fieldCode="DE" term="%22Clock+distribution+networks%22">Clock distribution networks</searchLink><br /><searchLink fieldCode="DE" term="%22Skewness+%28Probability+theory%29%22">Skewness (Probability theory)</searchLink><br /><searchLink fieldCode="DE" term="%22Electronic+systems%22">Electronic systems</searchLink><br /><searchLink fieldCode="DE" term="%22Electronic+industries%22">Electronic industries</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: Clock tree synthesis is the heart of the design and clock tree network robustness is one of the important quality metrics of the SoC design. With the technology advancement over past one-and-a-half decades, clock tree robustness has become an even more critical factor affecting SoC performance. There are some quality parameters which need to be kept in mind regarding clock tree design like minimum latency, minimum skew and duty cycle (Agarwal and Garg, 2012). A clock tree must be designed with these considerations and symmetrical cells having similar rise-fall delays should be used to build the clock tree. Keeping all the above parameters in mind, a clock tree has been designed for stitched CMOS image sensor. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of IUP Journal of Electrical & Electronics Engineering is the property of IUP Publications and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 6 StartPage: 7 Subjects: – SubjectFull: Complementary metal oxide semiconductors Type: general – SubjectFull: Clock distribution networks Type: general – SubjectFull: Skewness (Probability theory) Type: general – SubjectFull: Electronic systems Type: general – SubjectFull: Electronic industries Type: general Titles: – TitleFull: Design of Zero Skew Clock Tree for CMOS Image Sensor. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Kansal, Shubhi IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 10 Text: Oct2013 Type: published Y: 2013 Identifiers: – Type: issn-print Value: 2583519X Numbering: – Type: volume Value: 6 – Type: issue Value: 4 Titles: – TitleFull: IUP Journal of Electrical & Electronics Engineering Type: main |
| ResultId | 1 |
