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High speed testing of a four-bit RSFQ decimation digital filter.

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Bibliographic Details
Title: High speed testing of a four-bit RSFQ decimation digital filter.
Authors: Herr, Q.P.1, Gaj, K., Herr, A.M., Vukovic, N., Mancini, C.A., Bocko, M.F., Feldman, M.J.
Source: IEEE Transactions on Applied Superconductivity. 1997, Vol. 7 Issue 2, p2975-2978. 4p.
Subjects: Digital filters (Mathematics), Filters (Mathematics), Magnetic flux, Quantum mechanics, On-chip transformers
Abstract: We have developed a high speed test scheme for RSFQ circuits, in order to measure the maximum clock frequency of a four-bit RSFQ decimation digital filter (simulated to be 11 GHz). Our high speed test requires only a low speed interface and standard low-cost measurement equipment. Three auxiliary test units built of simple RSFQ circuits are used. A circular JTL structure generates an on-chip high speed clock with frequency adjustable from 4 to 16 GHz. A pseudo-random number generator with period 64 clock cycles provides parallel input to the filter. Finally, 12 four-bit acquisition shift registers collect output data. We have integrated all the above units on a single chip. The chip is initialized at low speed, run at high speed, and read out at low speed. Our testing scheme is superior to previously reported high-speed tests in the area of the added circuitry, in the requirements on high-speed input/output, in control, and in the parameters of the measurement equipment. The scheme can be easily adapted to test various RSFQ circuits. [ABSTRACT FROM PUBLISHER]
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Database: Engineering Source
Description
Abstract:We have developed a high speed test scheme for RSFQ circuits, in order to measure the maximum clock frequency of a four-bit RSFQ decimation digital filter (simulated to be 11 GHz). Our high speed test requires only a low speed interface and standard low-cost measurement equipment. Three auxiliary test units built of simple RSFQ circuits are used. A circular JTL structure generates an on-chip high speed clock with frequency adjustable from 4 to 16 GHz. A pseudo-random number generator with period 64 clock cycles provides parallel input to the filter. Finally, 12 four-bit acquisition shift registers collect output data. We have integrated all the above units on a single chip. The chip is initialized at low speed, run at high speed, and read out at low speed. Our testing scheme is superior to previously reported high-speed tests in the area of the added circuitry, in the requirements on high-speed input/output, in control, and in the parameters of the measurement equipment. The scheme can be easily adapted to test various RSFQ circuits. [ABSTRACT FROM PUBLISHER]
ISSN:10518223
DOI:10.1109/77.621942