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High speed testing of a four-bit RSFQ decimation digital filter.

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Title: High speed testing of a four-bit RSFQ decimation digital filter.
Authors: Herr, Q.P.1, Gaj, K., Herr, A.M., Vukovic, N., Mancini, C.A., Bocko, M.F., Feldman, M.J.
Source: IEEE Transactions on Applied Superconductivity. 1997, Vol. 7 Issue 2, p2975-2978. 4p.
Subjects: Digital filters (Mathematics), Filters (Mathematics), Magnetic flux, Quantum mechanics, On-chip transformers
Abstract: We have developed a high speed test scheme for RSFQ circuits, in order to measure the maximum clock frequency of a four-bit RSFQ decimation digital filter (simulated to be 11 GHz). Our high speed test requires only a low speed interface and standard low-cost measurement equipment. Three auxiliary test units built of simple RSFQ circuits are used. A circular JTL structure generates an on-chip high speed clock with frequency adjustable from 4 to 16 GHz. A pseudo-random number generator with period 64 clock cycles provides parallel input to the filter. Finally, 12 four-bit acquisition shift registers collect output data. We have integrated all the above units on a single chip. The chip is initialized at low speed, run at high speed, and read out at low speed. Our testing scheme is superior to previously reported high-speed tests in the area of the added circuitry, in the requirements on high-speed input/output, in control, and in the parameters of the measurement equipment. The scheme can be easily adapted to test various RSFQ circuits. [ABSTRACT FROM PUBLISHER]
Copyright of IEEE Transactions on Applied Superconductivity is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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DbLabel: Engineering Source
An: 93047446
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PubType: Academic Journal
PubTypeId: academicJournal
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  Data: High speed testing of a four-bit RSFQ decimation digital filter.
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  Data: <searchLink fieldCode="AR" term="%22Herr%2C+Q%2EP%2E%22">Herr, Q.P.</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Gaj%2C+K%2E%22">Gaj, K.</searchLink><br /><searchLink fieldCode="AR" term="%22Herr%2C+A%2EM%2E%22">Herr, A.M.</searchLink><br /><searchLink fieldCode="AR" term="%22Vukovic%2C+N%2E%22">Vukovic, N.</searchLink><br /><searchLink fieldCode="AR" term="%22Mancini%2C+C%2EA%2E%22">Mancini, C.A.</searchLink><br /><searchLink fieldCode="AR" term="%22Bocko%2C+M%2EF%2E%22">Bocko, M.F.</searchLink><br /><searchLink fieldCode="AR" term="%22Feldman%2C+M%2EJ%2E%22">Feldman, M.J.</searchLink>
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  Data: <searchLink fieldCode="DE" term="%22Digital+filters+%28Mathematics%29%22">Digital filters (Mathematics)</searchLink><br /><searchLink fieldCode="DE" term="%22Filters+%28Mathematics%29%22">Filters (Mathematics)</searchLink><br /><searchLink fieldCode="DE" term="%22Magnetic+flux%22">Magnetic flux</searchLink><br /><searchLink fieldCode="DE" term="%22Quantum+mechanics%22">Quantum mechanics</searchLink><br /><searchLink fieldCode="DE" term="%22On-chip+transformers%22">On-chip transformers</searchLink>
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  Data: We have developed a high speed test scheme for RSFQ circuits, in order to measure the maximum clock frequency of a four-bit RSFQ decimation digital filter (simulated to be 11 GHz). Our high speed test requires only a low speed interface and standard low-cost measurement equipment. Three auxiliary test units built of simple RSFQ circuits are used. A circular JTL structure generates an on-chip high speed clock with frequency adjustable from 4 to 16 GHz. A pseudo-random number generator with period 64 clock cycles provides parallel input to the filter. Finally, 12 four-bit acquisition shift registers collect output data. We have integrated all the above units on a single chip. The chip is initialized at low speed, run at high speed, and read out at low speed. Our testing scheme is superior to previously reported high-speed tests in the area of the added circuitry, in the requirements on high-speed input/output, in control, and in the parameters of the measurement equipment. The scheme can be easily adapted to test various RSFQ circuits. [ABSTRACT FROM PUBLISHER]
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  Data: <i>Copyright of IEEE Transactions on Applied Superconductivity is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Value: 10.1109/77.621942
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        Text: English
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      – SubjectFull: Filters (Mathematics)
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      – SubjectFull: Magnetic flux
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      – SubjectFull: Quantum mechanics
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      – SubjectFull: On-chip transformers
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              Text: 1997
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              Y: 1997
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