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Design and low speed testing of a four-bit RSFQ multiplier-accumulator.

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Title: Design and low speed testing of a four-bit RSFQ multiplier-accumulator.
Authors: Herr, Q.P.1, Vukovic, N., Mancini, C.A., Gaj, K., Qing Ke, Adler, V., Friedman, E.G., Krasniewski, A., Bocko, M.F., Feldman, M.J.
Source: IEEE Transactions on Applied Superconductivity. 1997, Vol. 7 Issue 2, p3168-3171. 4p.
Subjects: Multiplying circuits, Digital filters (Mathematics), Josephson junctions, Systolic array circuits, Hypres Inc.
Abstract: We have designed and RSFQ multiplier-accumulator, the central component of our decimation digital filter. The circuit consists of 38 synchronous RSFQ cells of six types arranged into a rectangular systolic array fed by one parallel input and one serial input. Timing is based on counter-flow clock distribution scheme with simulated maximum clock frequency of 11 GHz. The circuit, fabricated at Hypres, Inc., contains 1100 Josephson junctions, has power consumption less than 0.2 mW, and area less than 2.5 mm/sup 2/. The multiplier-accumulator has been tested at low frequency demonstrating full functionality and stable operation over a 24 hour testing period. This four-bit multiplier accumulator is one of the largest reported RSFQ circuits verified experimentally to date. [ABSTRACT FROM PUBLISHER]
Copyright of IEEE Transactions on Applied Superconductivity is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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DbLabel: Engineering Source
An: 93047492
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PubTypeId: academicJournal
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  Data: Design and low speed testing of a four-bit RSFQ multiplier-accumulator.
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  Data: <searchLink fieldCode="AR" term="%22Herr%2C+Q%2EP%2E%22">Herr, Q.P.</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Vukovic%2C+N%2E%22">Vukovic, N.</searchLink><br /><searchLink fieldCode="AR" term="%22Mancini%2C+C%2EA%2E%22">Mancini, C.A.</searchLink><br /><searchLink fieldCode="AR" term="%22Gaj%2C+K%2E%22">Gaj, K.</searchLink><br /><searchLink fieldCode="AR" term="%22Qing+Ke%22">Qing Ke</searchLink><br /><searchLink fieldCode="AR" term="%22Adler%2C+V%2E%22">Adler, V.</searchLink><br /><searchLink fieldCode="AR" term="%22Friedman%2C+E%2EG%2E%22">Friedman, E.G.</searchLink><br /><searchLink fieldCode="AR" term="%22Krasniewski%2C+A%2E%22">Krasniewski, A.</searchLink><br /><searchLink fieldCode="AR" term="%22Bocko%2C+M%2EF%2E%22">Bocko, M.F.</searchLink><br /><searchLink fieldCode="AR" term="%22Feldman%2C+M%2EJ%2E%22">Feldman, M.J.</searchLink>
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  Data: <searchLink fieldCode="JN" term="%22IEEE+Transactions+on+Applied+Superconductivity%22">IEEE Transactions on Applied Superconductivity</searchLink>. 1997, Vol. 7 Issue 2, p3168-3171. 4p.
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  Data: <searchLink fieldCode="DE" term="%22Multiplying+circuits%22">Multiplying circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Digital+filters+%28Mathematics%29%22">Digital filters (Mathematics)</searchLink><br /><searchLink fieldCode="DE" term="%22Josephson+junctions%22">Josephson junctions</searchLink><br /><searchLink fieldCode="DE" term="%22Systolic+array+circuits%22">Systolic array circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Hypres+Inc%2E%22">Hypres Inc.</searchLink>
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  Data: We have designed and RSFQ multiplier-accumulator, the central component of our decimation digital filter. The circuit consists of 38 synchronous RSFQ cells of six types arranged into a rectangular systolic array fed by one parallel input and one serial input. Timing is based on counter-flow clock distribution scheme with simulated maximum clock frequency of 11 GHz. The circuit, fabricated at Hypres, Inc., contains 1100 Josephson junctions, has power consumption less than 0.2 mW, and area less than 2.5 mm/sup 2/. The multiplier-accumulator has been tested at low frequency demonstrating full functionality and stable operation over a 24 hour testing period. This four-bit multiplier accumulator is one of the largest reported RSFQ circuits verified experimentally to date. [ABSTRACT FROM PUBLISHER]
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  Data: <i>Copyright of IEEE Transactions on Applied Superconductivity is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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              Text: 1997
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