Clock Distribution Area Reduction Using a Multiple-Valued Clocking Approach.

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Bibliographic Details
Title:	Clock Distribution Area Reduction Using a Multiple-Valued Clocking Approach.
Authors:	MENON, ROHIT P.¹ rmenon@smu.edu, THORNTON, MITCHELL A.¹ mitch@lyle.smu.edu
Source:	Journal of Multiple-Valued Logic & Soft Computing. 2014, Vol. 22 Issue 1-2, p21-39. 19p.
Subjects:	Clock distribution networks, Many-valued logic, Integrated circuit design, Field programmable gate arrays, Comparative studies, Logic circuits
Abstract:	Multi-phase clocking methods am well known and widely used in high-performance integrated circuit design. Such a scheme allows for relaxation of timing constraints among disjoint partitions of the logic circuitry since lower frequency local clocking is required as compared to the system clock frequency at the cost of increased clock distribution network area. The disadvantage is that multiple clock distribution trees are required, one for each clock domain or phase within the integrated circuit. Clock distribution networks have the highest fanout of any circuit within typical ICs and represent a significant amount of resource utilization. We devise a method that retains the advantages of multi-phase IC design, but utilizes a single global multiple-valued clock signal distribution network versus separate distribution networks for each phase in an ASIC or custom VLSI implementation. The technique requires a mini mal amount of modification to existing multiphase designs and is evaluated and compared to traditional multiphase designs. Furthermore, the approach is applicable to programmable logic (FPGA) implementations through distributing the multiple-valued clock signal using log2(N) distribution networks for an N-phase system. Experimental results are provided to validate and evaluate the approach. [ABSTRACT FROM AUTHOR]
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Database:	Engineering Source

Description
Abstract:	Multi-phase clocking methods am well known and widely used in high-performance integrated circuit design. Such a scheme allows for relaxation of timing constraints among disjoint partitions of the logic circuitry since lower frequency local clocking is required as compared to the system clock frequency at the cost of increased clock distribution network area. The disadvantage is that multiple clock distribution trees are required, one for each clock domain or phase within the integrated circuit. Clock distribution networks have the highest fanout of any circuit within typical ICs and represent a significant amount of resource utilization. We devise a method that retains the advantages of multi-phase IC design, but utilizes a single global multiple-valued clock signal distribution network versus separate distribution networks for each phase in an ASIC or custom VLSI implementation. The technique requires a mini mal amount of modification to existing multiphase designs and is evaluated and compared to traditional multiphase designs. Furthermore, the approach is applicable to programmable logic (FPGA) implementations through distributing the multiple-valued clock signal using log2(N) distribution networks for an N-phase system. Experimental results are provided to validate and evaluate the approach. [ABSTRACT FROM AUTHOR]
ISSN:	15423980