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Clock Distribution Area Reduction Using a Multiple-Valued Clocking Approach.

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Title: Clock Distribution Area Reduction Using a Multiple-Valued Clocking Approach.
Authors: MENON, ROHIT P.1 rmenon@smu.edu, THORNTON, MITCHELL A.1 mitch@lyle.smu.edu
Source: Journal of Multiple-Valued Logic & Soft Computing. 2014, Vol. 22 Issue 1-2, p21-39. 19p.
Subjects: Clock distribution networks, Many-valued logic, Integrated circuit design, Field programmable gate arrays, Comparative studies, Logic circuits
Abstract: Multi-phase clocking methods am well known and widely used in high-performance integrated circuit design. Such a scheme allows for relaxation of timing constraints among disjoint partitions of the logic circuitry since lower frequency local clocking is required as compared to the system clock frequency at the cost of increased clock distribution network area. The disadvantage is that multiple clock distribution trees are required, one for each clock domain or phase within the integrated circuit. Clock distribution networks have the highest fanout of any circuit within typical ICs and represent a significant amount of resource utilization. We devise a method that retains the advantages of multi-phase IC design, but utilizes a single global multiple-valued clock signal distribution network versus separate distribution networks for each phase in an ASIC or custom VLSI implementation. The technique requires a mini mal amount of modification to existing multiphase designs and is evaluated and compared to traditional multiphase designs. Furthermore, the approach is applicable to programmable logic (FPGA) implementations through distributing the multiple-valued clock signal using log2(N) distribution networks for an N-phase system. Experimental results are provided to validate and evaluate the approach. [ABSTRACT FROM AUTHOR]
Copyright of Journal of Multiple-Valued Logic & Soft Computing is the property of Old City Publishing, Inc. and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
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  Data: Clock Distribution Area Reduction Using a Multiple-Valued Clocking Approach.
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  Data: <searchLink fieldCode="DE" term="%22Clock+distribution+networks%22">Clock distribution networks</searchLink><br /><searchLink fieldCode="DE" term="%22Many-valued+logic%22">Many-valued logic</searchLink><br /><searchLink fieldCode="DE" term="%22Integrated+circuit+design%22">Integrated circuit design</searchLink><br /><searchLink fieldCode="DE" term="%22Field+programmable+gate+arrays%22">Field programmable gate arrays</searchLink><br /><searchLink fieldCode="DE" term="%22Comparative+studies%22">Comparative studies</searchLink><br /><searchLink fieldCode="DE" term="%22Logic+circuits%22">Logic circuits</searchLink>
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  Data: Multi-phase clocking methods am well known and widely used in high-performance integrated circuit design. Such a scheme allows for relaxation of timing constraints among disjoint partitions of the logic circuitry since lower frequency local clocking is required as compared to the system clock frequency at the cost of increased clock distribution network area. The disadvantage is that multiple clock distribution trees are required, one for each clock domain or phase within the integrated circuit. Clock distribution networks have the highest fanout of any circuit within typical ICs and represent a significant amount of resource utilization. We devise a method that retains the advantages of multi-phase IC design, but utilizes a single global multiple-valued clock signal distribution network versus separate distribution networks for each phase in an ASIC or custom VLSI implementation. The technique requires a mini mal amount of modification to existing multiphase designs and is evaluated and compared to traditional multiphase designs. Furthermore, the approach is applicable to programmable logic (FPGA) implementations through distributing the multiple-valued clock signal using log2(N) distribution networks for an N-phase system. Experimental results are provided to validate and evaluate the approach. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
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  Data: <i>Copyright of Journal of Multiple-Valued Logic & Soft Computing is the property of Old City Publishing, Inc. and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Text: English
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        PageCount: 19
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      – SubjectFull: Clock distribution networks
        Type: general
      – SubjectFull: Many-valued logic
        Type: general
      – SubjectFull: Integrated circuit design
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      – SubjectFull: Field programmable gate arrays
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      – SubjectFull: Comparative studies
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      – SubjectFull: Logic circuits
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              Text: 2014
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