High-Speed Systolic VLSI Architecture for 2-D Forward Lifting-Based DWT.

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Bibliographic Details
Title:	High-Speed Systolic VLSI Architecture for 2-D Forward Lifting-Based DWT.
Authors:	Usha Bhanu, N.¹ bhanu.usha@rediffmail.com, Chilambuchelvan, A.² Chill97@gmail.com
Source:	Arabian Journal for Science & Engineering (Springer Science & Business Media B.V. ). Aug2014, Vol. 39 Issue 8, p6125-6135. 11p.
Subjects:	Discrete wavelet transforms, Systolic array circuits, Field programmable gate arrays, Computer engineering, Computer science
Abstract (English):	In this paper, an efficient approach to design a 2-D systolic array for high-speed implementation of block-based lifting lossy 9/7 wavelet filter is proposed. The inherent advantage of the in place computation of the lifting-based discrete wavelet transform over the conventional convolution method makes it suitable for efficient hardware implementation with lower computational complexity. The row processor consists of processing elements arranged in a systolic manner, and for column processing, the lifting steps are computed concurrently, by mapping the coefficients to the same systolic arrays, using the cyclic symmetry property of the block of input image coefficients. The advantage of the discussed architecture is that it does not require additional memory for storing the intermediate coefficients. The functionality of the processing element in the systolic array improves the speed, by having the critical path delay of one multiplier and two adders computational time. The area efficient, high-speed design of the lifting algorithm is coded in hardware description language and implemented in Altera cyclone II field programmable gate arrays (FPGA). The implemented results show that the systolic architecture achieves a high speed of 260MHz with a lower accessing time of 0.246μs, when compared to other existing architectures, and reaches a speed performance suitable for real-time multimedia applications. This conceptual design of systolic arrays can be used as IP core in FPGA-based reconfigurable coprocessors. [ABSTRACT FROM AUTHOR]
Abstract (Arabic):	[MediaObject not available: see fulltext.] [ABSTRACT FROM AUTHOR]
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Database:	Engineering Source

Description
Abstract:	In this paper, an efficient approach to design a 2-D systolic array for high-speed implementation of block-based lifting lossy 9/7 wavelet filter is proposed. The inherent advantage of the in place computation of the lifting-based discrete wavelet transform over the conventional convolution method makes it suitable for efficient hardware implementation with lower computational complexity. The row processor consists of processing elements arranged in a systolic manner, and for column processing, the lifting steps are computed concurrently, by mapping the coefficients to the same systolic arrays, using the cyclic symmetry property of the block of input image coefficients. The advantage of the discussed architecture is that it does not require additional memory for storing the intermediate coefficients. The functionality of the processing element in the systolic array improves the speed, by having the critical path delay of one multiplier and two adders computational time. The area efficient, high-speed design of the lifting algorithm is coded in hardware description language and implemented in Altera cyclone II field programmable gate arrays (FPGA). The implemented results show that the systolic architecture achieves a high speed of 260MHz with a lower accessing time of 0.246μs, when compared to other existing architectures, and reaches a speed performance suitable for real-time multimedia applications. This conceptual design of systolic arrays can be used as IP core in FPGA-based reconfigurable coprocessors. [ABSTRACT FROM AUTHOR]
ISSN:	2193567X
DOI:	10.1007/s13369-014-1208-2