High-Speed Systolic VLSI Architecture for 2-D Forward Lifting-Based DWT.
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| Title: | High-Speed Systolic VLSI Architecture for 2-D Forward Lifting-Based DWT. |
|---|---|
| Authors: | Usha Bhanu, N.1 bhanu.usha@rediffmail.com, Chilambuchelvan, A.2 Chill97@gmail.com |
| Source: | Arabian Journal for Science & Engineering (Springer Science & Business Media B.V. ). Aug2014, Vol. 39 Issue 8, p6125-6135. 11p. |
| Subjects: | Discrete wavelet transforms, Systolic array circuits, Field programmable gate arrays, Computer engineering, Computer science |
| Abstract (English): | In this paper, an efficient approach to design a 2-D systolic array for high-speed implementation of block-based lifting lossy 9/7 wavelet filter is proposed. The inherent advantage of the in place computation of the lifting-based discrete wavelet transform over the conventional convolution method makes it suitable for efficient hardware implementation with lower computational complexity. The row processor consists of processing elements arranged in a systolic manner, and for column processing, the lifting steps are computed concurrently, by mapping the coefficients to the same systolic arrays, using the cyclic symmetry property of the block of input image coefficients. The advantage of the discussed architecture is that it does not require additional memory for storing the intermediate coefficients. The functionality of the processing element in the systolic array improves the speed, by having the critical path delay of one multiplier and two adders computational time. The area efficient, high-speed design of the lifting algorithm is coded in hardware description language and implemented in Altera cyclone II field programmable gate arrays (FPGA). The implemented results show that the systolic architecture achieves a high speed of 260MHz with a lower accessing time of 0.246μs, when compared to other existing architectures, and reaches a speed performance suitable for real-time multimedia applications. This conceptual design of systolic arrays can be used as IP core in FPGA-based reconfigurable coprocessors. [ABSTRACT FROM AUTHOR] |
| Abstract (Arabic): | [MediaObject not available: see fulltext.] [ABSTRACT FROM AUTHOR] |
| Copyright of Arabian Journal for Science & Engineering (Springer Science & Business Media B.V. ) is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
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| Header | DbId: egs DbLabel: Engineering Source An: 97178536 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: High-Speed Systolic VLSI Architecture for 2-D Forward Lifting-Based DWT. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Usha+Bhanu%2C+N%2E%22">Usha Bhanu, N.</searchLink><relatesTo>1</relatesTo><i> bhanu.usha@rediffmail.com</i><br /><searchLink fieldCode="AR" term="%22Chilambuchelvan%2C+A%2E%22">Chilambuchelvan, A.</searchLink><relatesTo>2</relatesTo><i> Chill97@gmail.com</i> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Arabian+Journal+for+Science+%26+Engineering+%28Springer+Science+%26+Business+Media+B%2EV%2E+%29%22">Arabian Journal for Science & Engineering (Springer Science & Business Media B.V. )</searchLink>. Aug2014, Vol. 39 Issue 8, p6125-6135. 11p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Discrete+wavelet+transforms%22">Discrete wavelet transforms</searchLink><br /><searchLink fieldCode="DE" term="%22Systolic+array+circuits%22">Systolic array circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Field+programmable+gate+arrays%22">Field programmable gate arrays</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+engineering%22">Computer engineering</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+science%22">Computer science</searchLink> – Name: Abstract Label: Abstract (English) Group: Ab Data: In this paper, an efficient approach to design a 2-D systolic array for high-speed implementation of block-based lifting lossy 9/7 wavelet filter is proposed. The inherent advantage of the in place computation of the lifting-based discrete wavelet transform over the conventional convolution method makes it suitable for efficient hardware implementation with lower computational complexity. The row processor consists of processing elements arranged in a systolic manner, and for column processing, the lifting steps are computed concurrently, by mapping the coefficients to the same systolic arrays, using the cyclic symmetry property of the block of input image coefficients. The advantage of the discussed architecture is that it does not require additional memory for storing the intermediate coefficients. The functionality of the processing element in the systolic array improves the speed, by having the critical path delay of one multiplier and two adders computational time. The area efficient, high-speed design of the lifting algorithm is coded in hardware description language and implemented in Altera cyclone II field programmable gate arrays (FPGA). The implemented results show that the systolic architecture achieves a high speed of 260MHz with a lower accessing time of 0.246μs, when compared to other existing architectures, and reaches a speed performance suitable for real-time multimedia applications. This conceptual design of systolic arrays can be used as IP core in FPGA-based reconfigurable coprocessors. [ABSTRACT FROM AUTHOR] – Name: Abstract Label: Abstract (Arabic) Group: Ab Data: [MediaObject not available: see fulltext.] [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of Arabian Journal for Science & Engineering (Springer Science & Business Media B.V. ) is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1007/s13369-014-1208-2 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 11 StartPage: 6125 Subjects: – SubjectFull: Discrete wavelet transforms Type: general – SubjectFull: Systolic array circuits Type: general – SubjectFull: Field programmable gate arrays Type: general – SubjectFull: Computer engineering Type: general – SubjectFull: Computer science Type: general Titles: – TitleFull: High-Speed Systolic VLSI Architecture for 2-D Forward Lifting-Based DWT. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Usha Bhanu, N. – PersonEntity: Name: NameFull: Chilambuchelvan, A. IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 08 Text: Aug2014 Type: published Y: 2014 Identifiers: – Type: issn-print Value: 2193567X Numbering: – Type: volume Value: 39 – Type: issue Value: 8 Titles: – TitleFull: Arabian Journal for Science & Engineering (Springer Science & Business Media B.V. ) Type: main |
| ResultId | 1 |
