Modified DEC for Short BCH Codes for Parallel Correction of 3-Bit Error with High Decoding Efficiency.

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Bibliographic Details
Title:	Modified DEC for Short BCH Codes for Parallel Correction of 3-Bit Error with High Decoding Efficiency.
Authors:	Tabassum, Hiba¹ hibatabassum6@gmail.com, Kumar, B. Kiran² b.kirankumar@lords.ac.in, Jabirullah, Mohammad³ drjabirullah@lords.ac.in
Source:	Turkish Online Journal of Qualitative Inquiry. 2021, Vol. 12 Issue 10, p1017-1028. 12p.
Subject Terms:	Bit error rate, Energy consumption
Abstract:	This paper describes a new Bose - Chaudhuri - Hocquenghem (BCH) code decoder for error correction in expanding memory that has a high decoding capacity while using less power. For the DEC-TED BCH code, we propose an adaptive error correction method that identifies the amount of mistakes in a codeword immediately after syndrome generation and uses a different error correction algorithm based on the error situation. This technique improves decoding performance. Adaptive error correction lowers average decoding time and energy consumption substantially by increasing decoding performance. Erroneous transitions in error-finding blocks are caused by syndrome vector glitches, which may be removed to save power. The proposed decoders for the (79, 64, 6) BCH code have an average decoding latency of only 37 percent -48 percent and achieve a power reduction of over 70 percent compared to the conventional fully parallel decoder for the 104-102 raw bit error rate, according to synthesis results using an industrycompatible 65-nm technology library. [ABSTRACT FROM AUTHOR]
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Database:	Education Research Complete

Description
Abstract:	This paper describes a new Bose - Chaudhuri - Hocquenghem (BCH) code decoder for error correction in expanding memory that has a high decoding capacity while using less power. For the DEC-TED BCH code, we propose an adaptive error correction method that identifies the amount of mistakes in a codeword immediately after syndrome generation and uses a different error correction algorithm based on the error situation. This technique improves decoding performance. Adaptive error correction lowers average decoding time and energy consumption substantially by increasing decoding performance. Erroneous transitions in error-finding blocks are caused by syndrome vector glitches, which may be removed to save power. The proposed decoders for the (79, 64, 6) BCH code have an average decoding latency of only 37 percent -48 percent and achieve a power reduction of over 70 percent compared to the conventional fully parallel decoder for the 104-102 raw bit error rate, according to synthesis results using an industrycompatible 65-nm technology library. [ABSTRACT FROM AUTHOR]
ISSN:	13096591