Optimising digital combinational circuit using particle swarm optimisation technique.

Saved in:

Bibliographic Details
Title:	Optimising digital combinational circuit using particle swarm optimisation technique.
Authors:	Ushie, James Ogri¹ ushjames@yahoo.com, Abebe Etim, Obu Joseph¹ abebeobu@yahoo.com, prosper, Iniobong¹ ini2etim@yahoo.com
Source:	Latin-American Journal of Physics Education. Mar2012, Vol. 6 Issue 1, p72-77. 6p.
Subject Terms:	Maxima & minima, Particle swarm optimization, Electronic circuits, Mathematical variables, Mathematical optimization
Abstract (English):	Human methods of circuit minimisation are tedious and limited to systems with four or five numbers of inputs. In order to save time and labour involved in designing digital combinational logic circuit, a standard algorithm that is suitable for digital combinational logic circuit with little modification which handle circuit with more than five inputs variables is developed. Employing MATLAB, the circuits were coded into particles using Particle Swarm Optimisation (PSO) techniques. This was then used to optimise a full-adder circuit. The result obtained, after optimisation for full-adder circuit using PSO technique is shown to have a minimum number of gates (five gates) compared to human designer method which has six gates. [ABSTRACT FROM AUTHOR]
Abstract (Spanish):	Los métodos humanos de minimización de circuitos son tediosos y se limita a los sistemas con cuatro o cinco números de entrada. Con el fin de ahorrar tiempo y mano de obra involucrada en el diseño de circuitos digitales de lógica combinatoria, se desarrollado un algoritmo estándar que es adecuado para el circuito digital de lógica combinatoria con muy pocas modificaciones que se encarga del circuito con más de cinco variables de entrada. Con el empleo de MATLAB, los circuitos fueron codificados en partículas usando técnicas de optimización por enjambre de partículas (PSO). Este se utilizó entonces para optimizar un circuito sumador completo. El resultado obtenido, después de la optimización de circuito sumador completo utilizando la técnica de PSO se demuestra que tienen un número mínimo de puertas (cinco puertas) en comparación con el método de diseño humano que tiene seis puertas. [ABSTRACT FROM AUTHOR]
	Copyright of Latin-American Journal of Physics Education is the property of Latin-American Physics Education Network and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database:	Education Research Complete

Description
Abstract:	Human methods of circuit minimisation are tedious and limited to systems with four or five numbers of inputs. In order to save time and labour involved in designing digital combinational logic circuit, a standard algorithm that is suitable for digital combinational logic circuit with little modification which handle circuit with more than five inputs variables is developed. Employing MATLAB, the circuits were coded into particles using Particle Swarm Optimisation (PSO) techniques. This was then used to optimise a full-adder circuit. The result obtained, after optimisation for full-adder circuit using PSO technique is shown to have a minimum number of gates (five gates) compared to human designer method which has six gates. [ABSTRACT FROM AUTHOR]
ISSN:	18709095