A Comparative Study of SiC Power Module with Reduced Footprint for High Power Density Applications.
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| Title: | A Comparative Study of SiC Power Module with Reduced Footprint for High Power Density Applications. |
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| Authors: | Fang, Xinyi1,2 (AUTHOR), Che, Liming1,2 (AUTHOR), Li, Cancan1,2 (AUTHOR), Lin, Yongtai1,2 (AUTHOR), Mao, Yinjie1,2 (AUTHOR), Lei, Guangyin1,2 (AUTHOR) guangyinlei@fudan.edu.cn |
| Source: | Energies (19961073). Apr2026, Vol. 19 Issue 7, p1693. 16p. |
| Subject Terms: | *Packaging design, *Thermal resistance, *Electric inductance, *Power density, *Substrates (Materials science), *Mutual inductance |
| Abstract: | Driven by the increasing demand for high power density in modern power electronic converters, this paper proposes two novel packaging designs based on the concept of an overlaying chip placement structure, including the design with a two-layer substrate (designated as M2) and the one with a three-layer substrate overlaying structure (designated as M3). Electrical and thermal simulations demonstrate that M2 achieves a 32.78% volume reduction while incurring a 12.70% increase in average thermal resistance, and a 5.72% reduction in power loop parasitic inductance compared to the conventional packaging design (designated as M1), representing a balance between compact packaging and electrothermal performance. Meanwhile, M3 achieves an ultra-low loop inductance of 2.02 nH thanks to the mutual inductance cancellation effect; however, the physical volume is increased by 38.17%, and the thermal resistance is reduced by 1.59% compared to the M1 design. The prototype of the M1 power module has been fabricated for experimental validation. Double-pulse testing and steady-state thermal resistance measurements are conducted based on the M1 prototype to confirm the accuracy of the simulation model. [ABSTRACT FROM AUTHOR] |
| Database: | Energy & Power Source |
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| Abstract: | Driven by the increasing demand for high power density in modern power electronic converters, this paper proposes two novel packaging designs based on the concept of an overlaying chip placement structure, including the design with a two-layer substrate (designated as M2) and the one with a three-layer substrate overlaying structure (designated as M3). Electrical and thermal simulations demonstrate that M2 achieves a 32.78% volume reduction while incurring a 12.70% increase in average thermal resistance, and a 5.72% reduction in power loop parasitic inductance compared to the conventional packaging design (designated as M1), representing a balance between compact packaging and electrothermal performance. Meanwhile, M3 achieves an ultra-low loop inductance of 2.02 nH thanks to the mutual inductance cancellation effect; however, the physical volume is increased by 38.17%, and the thermal resistance is reduced by 1.59% compared to the M1 design. The prototype of the M1 power module has been fabricated for experimental validation. Double-pulse testing and steady-state thermal resistance measurements are conducted based on the M1 prototype to confirm the accuracy of the simulation model. [ABSTRACT FROM AUTHOR] |
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| ISSN: | 19961073 |
| DOI: | 10.3390/en19071693 |
